LAN8740A Datasheet, PDF (58/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
4.0 REGISTER DESCRIPTIONS
This chapter describes the various Control and Status Registers (CSRs) and MDIO Manageable Device (MMD) Regis-
ters. The CSRs follow the IEEE 802.3 (clause 22.2.4) management register set. The MMD registers adhere to the IEEE
802.3-2008 45.2 MDIO Interface Registers specification. All functionality and bit definitions comply with these stan-
dards. The IEEE 802.3 specified register index (in decimal) is included with each CSR definition, allowing for addressing
of these registers via the Serial Management Interface (SMI) protocol. MMD registers are accessed indirectly via the
MMD Access Control Register and MMD Access Address/Data Register CSRs.
4.1 Register Nomenclature
Table 4-1 describes the register bit attribute notation used throughout this document.
TABLE 4-1: REGISTER BIT TYPES
Register Bit Type Notation
Register Bit Description
R
W
RO
WO
WC
WAC
RC
LL
LH
SC
SS
RO/LH
NASR
RESERVED
Read: A register or bit with this attribute can be read.
Write: A register or bit with this attribute can be written.
Read only: Writes have no effect.
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Clear: Writing a one clears the value. Writing a zero has no effect
Write Anything to Clear: Writing anything clears the value.
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: Clear on read of register.
Latch High: Clear on read of register.
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it
is read, the bit will either remain high if the high condition remains, or will go low if the
high condition has been removed. If the bit has not been read, the bit will remain high
regardless of a change to the high condition. This mode is used in some Ethernet PHY
registers.
Not Affected by Software Reset: The state of NASR bits do not change on assertion
of a software reset.
Reserved Field: Reserved fields must be written with zeros to ensure future compati-
bility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combined. Some examples of this are shown below:
• R/W: Can be written. Will return current setting on a read.
• R/WAC: Will return current setting on a read. Writing anything clears the bit.
DS00001987A-page 58
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