LAN8740A Datasheet, PDF (30/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.6 Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This
interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events
are detected as setup by the Interrupt Mask Register.
The nINT signal can be selected to output on three different pins:
• nINT/TXER/TXD4
(See Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration" for configuration information)
• LED1
(See Section 3.8.1, "LEDs" for configuration information)
• LED2
(See Section 3.8.1, "LEDs" for configuration information)
The device’s interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both
systems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-
assert the nINT interrupt output. These modes are detailed in the following subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative
interrupt mode requires setup after a power-up or hard reset.
Note: In addition to the main interrupts described in this section, an nPME pin is provided exclusively for WoL
specific interrupts. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional information on nPME.
Note:
Due to the multiplexing of nINT and TXER on the same pin, when EEE and WoL are both enabled, nINT
and/or nPME must be multiplexed on LED1 and/or LED2. Refer to Section 3.8.1, "LEDs" and Section 3.8.4,
"Wake on LAN (WoL)" for additional information.
DS00001987A-page 30
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