LAN8740A Datasheet, PDF (41/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.8.4.1 Perfect DA (Destination Address) Detection
When enabled, the Perfect DA detection mode allows the triggering of the nINT or nPME pin when a frame with the
destination address matching the address stored in the MAC Receive Address A Register (RX_ADDRA), MAC Receive
Address B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC) is received. The frame must
also pass the FCS and packet length check.
As an example, the Host system must perform the following steps to enable the device to assert nINT on detection of a
Perfect DA WoL event:
1. Set the desired MAC address to cause the wake event in the MAC Receive Address A Register (RX_ADDRA),
MAC Receive Address B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC).
2. Set the Perfect DA Wakeup Enable (PFDA_EN) bit of the Wakeup Control and Status Register (WUCSR) to
enable Perfect DA detection.
3. Set bit 8 (WoL event indicator) in the Interrupt Mask Register to enable WoL events to trigger assertion of the
nINT interrupt pin.
When a match is triggered, the nINT interrupt pin will be asserted, bit 8 of the Interrupt Source Flag Register will be set,
and the Perfect DA Frame Received (PFDA_FR) bit of the Wakeup Control and Status Register (WUCSR) will be set.
Note: Alternatively, the LED1/nINT/nPME, LED2/nINT/nPME, or RXD2/nPME pin can be used to indicate a WoL
event. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional information.
3.8.4.2 Broadcast Detection
When enabled, the Broadcast detection mode allows the triggering of the nINT or nPME pin when a frame with the des-
tination address value of FF FF FF FF FF FF is received. The frame must also pass the FCS and packet length check.
As an example, the Host system must perform the following steps to enable the device to assert nINT on detection of a
Broadcast WoL event:
1. Set the Broadcast Wakeup Enable (BCST_EN) bit of the Wakeup Control and Status Register (WUCSR) to
enable Broadcast detection.
2. Set bit 8 (WoL event indicator) in the Interrupt Mask Register to enable WoL events to trigger assertion of the
nINT interrupt pin.
When a match is triggered, the nINT interrupt pin will be asserted, bit 8 of the Interrupt Source Flag Register will be set,
and the Broadcast Frame Received (BCAST_FR) bit of the Wakeup Control and Status Register (WUCSR) will be set.
Note: Alternatively, the LED1/nINT/nPME, LED2/nINT/nPME, or RXD2/nPME pin can be used to indicate a WoL
event. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional information.
3.8.4.3 Magic Packet Detection
When enabled, the Magic Packet detection mode allows the triggering of the nINT or nPME pin when a Magic Packet
frame is received. A Magic Packet is a frame addressed to the device - either a unicast to the programmed address, or
a broadcast - which contains the pattern 48’h FF_FF_FF_FF_FF_FF after the destination and source address field, fol-
lowed by 16 repetitions of the desired MAC address (loaded into the MAC Receive Address A Register (RX_ADDRA),
MAC Receive Address B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC)) without any
breaks or interruptions. In case of a break in the 16 address repetitions, the logic scans for the 48’h
FF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must
be preceded by the synchronization stream. The frame must also pass the FCS check and packet length checking.
As an example, if the desired address is 00h 11h 22h 33h 44h 55h, then the logic scans for the following data sequence
in an Ethernet frame:
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…FCS
 2013-2015 Microchip Technology Inc.
DS00001987A-page 41