LAN8740A Datasheet, PDF (74/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
4.2.15 TDR PATTERNS/DELAY CONTROL REGISTER
Index (In Decimal): 24
Size:
16 bits
Bits
15
14:12
11:6
5:0
Description
TDR Delay In
0 = Line break time is 2 ms.
1 = The device uses TDR Line Break Counter to increase the line break time
before starting TDR.
TDR Line Break Counter
When TDR Delay In is 1, this field specifies the increase in line break time in
increments of 256 ms, up to 2 seconds.
TDR Pattern High
This field specifies the data pattern sent in TDR mode for the high cycle.
TDR Pattern Low
This field specifies the data pattern sent in TDR mode for the low cycle.
Type
R/W
NASR
R/W
NASR
R/W
NASR
R/W
NASR
Default
0b
000b
101110b
011101b
DS00001987A-page 74
 2013-2015 Microchip Technology Inc.