LAN8740A Datasheet, PDF (32/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.6.2 ALTERNATE INTERRUPT SYSTEM
The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to “1”. In this
mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3-4). To Clear an interrupt,
either clear the corresponding bit in the Interrupt Mask Register to deassert the nINT output, or clear the interrupt
source, and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause
the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If
the Condition to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the Condition
to deassert is false, then the Interrupt Source Flag remains set, and the nINT remains asserted.
For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable is
plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nINT will be asserted low. To de-
assert the nINT interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing the
cable and then writing a ‘1’ to the INT7 bit in the Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt
Mask Register).
TABLE 3-4: ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE
Mask
30.8
30.7
30.6
30.5
30.4
30.3
30.2
30.1
Interrupt Source Flag
Interrupt Source
29.8
WoL
3.32784.7:4
nPME
29.7 ENERGYON
17.1
29.6 Auto-Negotiation
1.5
Complete
29.5 Remote Fault
1.4
Detected
29.4
Link Down
1.2
29.3 Auto-Negotiation
5.14
LP Acknowledge
29.2 Parallel Detection
6.4
Fault
29.1 Auto-Negotiation
6.1
Page Received
ENERGYON
Auto-Negotiate
Complete
Remote Fault
Link Status
Acknowledge
Parallel Detec-
tion Fault
Page Received
Event to
Assert nINT
Rising
3.32784.7:4
or’ed
Rising 17.1
Rising 1.5
Condition to Bit to Clear
DeAssert
nINT
3.32784.7:4
29.8
all low
17.1 low
29.7
1.5 low
29.6
Rising 1.4
1.4 low
29.5
Falling 1.2
1.2 high
29.4
Rising 5.14
5.14 low
29.3
Rising 6.4
6.4 low
29.2
Rising 6.1
6.1 low
29.1
Note:
The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-
sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no
signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.
DS00001987A-page 32
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