LAN8740A Datasheet, PDF (21/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.1.2.7 Receive Data Valid Signal
The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the
RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD
is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure
or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII
mode).
FIGURE 3-3:
RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS
CLEAR-TEXT
J
K
5
5
5
D data data data data T
R Idle
RX_CLK
RX_DV
RXD
5 5 5 5 5 D data data data data
3.1.2.8 Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0
through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary
data is driven onto the RXD[3:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being
decoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the
Valid Data signal is not yet asserted when the bad SSD error occurs.
3.1.2.9 100M Receive Data Across the MII/RMII Interface
In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the controller at a rate
of 25 MHz. The controller samples the data on the rising edge of RXCLK. To ensure that the setup and hold require-
ments are met, the nibbles are clocked out of the transceiver on the falling edge of RXCLK. RXCLK is the 25 MHz output
clock for the MII bus. It is recovered from the received data to clock the RXD bus. If there is no received signal, it is
derived from the system reference clock (XTAL1/CLKIN).
When tracking the received data, RXCLK has a maximum jitter of 0.8 ns (provided that the jitter of the input clock,
XTAL1/CLKIN, is below 100 ps).
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate
of 50 MHz. The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup
and hold requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN
(REF_CLK).
3.1.3 10BASE-T TRANSMIT
Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the
MII at a rate of 2.5 MHz and converts them to a 10 Mbps serial data stream. The data stream is then Manchester-
encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
• MII (digital)
• TX 10M (digital)
• 10M Transmitter (analog)
• 10M PLL (analog)
 2013-2015 Microchip Technology Inc.
DS00001987A-page 21