LAN8740A Datasheet, PDF (31/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.6.1 PRIMARY INTERRUPT SYSTEM
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The
Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the cor-
responding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT
output will be asserted. When the corresponding event to deassert nINT is true, then the nINT will be de-asserted.
TABLE 3-3: INTERRUPT MANAGEMENT TABLE
Mask Interrupt Source Flag
Interrupt Source
Event to Assert
nINT
Event to
De-Assert nINT
30.8 29.8
WoL
3.32784.7:4
nPME
Rising
3.32784.7:4
or’ed together
3.32784.7:4 or’ed together
low or reading register 29
30.7 29.7 ENERGYON
17.1
ENERGYON Rising 17.1 (see
Falling 17.1 or
Note 1)
Reading register 29
30.6 29.6 Auto-Negotiation
1.5
Auto-Negotiate
Rising 1.5
Complete
Complete
Falling 1.5 or
Reading register 29
30.5 29.5 Remote Fault
Detected
1.4
Remote Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4 29.4
Link Down
1.2
Link Status
Falling 1.2
Reading register 1 or
Reading register 29
30.3 29.3 Auto-Negotiation
5.14
LP Acknowledge
Acknowledge
Rising 5.14
Falling 5.14 or
Reading register 29
30.2 29.2 Parallel Detection
6.4
Fault
Parallel Detec-
tion Fault
Rising 6.4
Falling 6.4 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate or
Link down
30.1 29.1 Auto-Negotiation
Page Received
6.1
Page Received
Rising 6.1
Falling 6.1 or
Reading register 6, or
Reading register 29, or
Re-Auto Negotiate, or
Link down.
Note 1: If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert
for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent
an unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the
ENERGYON interrupt service routine.
Note:
The ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-
sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no
signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.
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DS00001987A-page 31