LAN8740A Datasheet, PDF (130/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
APPENDIX A: REVISION HISTORY
REVISION LEVEL
& DATE
SECTION/FIGURE/ENTRY
CORRECTION
Revision A
(09-07-15)
Rev. 1.1
(05-10-13)
Replaces the previous SMSC version Rev. 1.1
• Added Note and Trademark page
• Added Worldwide Sales and Services page
• Added Product Identification System
• Changed ‘QFN’ to ‘VQFN’
Chapter 2, "Pin Description and
Configuration"
• Figure 2-1: rotated 90° cw
• Table 2-3, “Serial Management Interface (SMI)
Pins”: Changed “VIS/VOD8 (PU)” to “VIS/VO8
(PU)”
Section 4.1, "Register Nomenclature"
Table 4-1, “Register Bit Types”, register bit
description for byte type notification ‘W’: Changed
“read” to ‘written”
Section 5.6.4, "RMII Interface Timing"
Section 5.7, "Clock Circuit"
Updated RMII timing table: Updated REF_CLK In
mode t_oval max from “14.0 ns” to “15.0 ns”
Added new 100 µW crystal specifications and circuit
diagram. The section is now split into two
subsections, one for 300 µW crystals and the other
for 100 µW crystals.
Chapter 6, "Package Outline"
Updated package outline drawing information
General
• Changed part numbers from
“LAN8740/LAN8740i” to
“LAN8740A/LAN8740Ai”
• Updated ordering information
• Updated figures
Cover
Added new bullet under Highlights section:
“Deterministic 100 Mb internal loopback latency (MII
Mode)”
Chapter 2, "Pin Description and
Configuration", Table 2-1, “MII/RMII
Signals”
Changed buffer type from “VIS (PU)” to “VIS”
Chapter 2, "Pin Description and
Configuration", Table 2-3, “Serial
Management Interface (SMI) Pins”
• Added pull-up to MDIO buffer type description
• Changed “VIS/VOD8 (PU)” to “VIS/VO8 (PU)”
Section 3.3, "HP Auto-MDIX Support" Changed “100BASE-T” to “100BASE-TX”
Section 3.4.2.1, "CRS_DV - Carrier
Sense/Receive Data Valid"
Changed “100BASE-X” to “100BASE-TX”
Section 3.5, "Serial Management
Interface (SMI)"
Removed sentence stating “Non-supported registers
(such as 7 to 15) will be read as hexadecimal
“FFFF”.
Section 3.8.11, "Cable Diagnostics"
Updated section with additional operation details
Section 3.8.12.1, "Near-end Loopback" Added cross-reference to 100 Mbps internal
loopback timing section
, "," on page 58
Removed
- TDR Channel Threshold Maximum Register
- TDR Wait Counter Threshold Register
- TDR TX Pattern Generator Divider Register
Section 4.2.2, "Basic Status Register" Updated definitions of bits 10:8
Section 4.2.18, "Special Control/Status Updated bit 11 definition
Indications Register"
Section 4.2.22, "PHY Special
Control/Status Register"
Updated bit 6 definition
DS00001987A-page 130
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