LAN8740A Datasheet, PDF (118/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
5.6.2 POWER-ON nRST & CONFIGURATION STRAP TIMING
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware
reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than
t_rstia. The nRST pin can be asserted at any time, but must not be deasserted before t_purstd after all external power sup-
plies have reached operational levels. In order for valid configuration strap values to be read at power-up, the t_css and
t_csh timing constraints must be followed. Refer to Section 3.8.7, "Resets" for additional information.
FIGURE 5-2:
POWER-ON nRST & CONFIGURATION STRAP TIMING
All External
Vopp
Power Supplies
nRST
t_purstv
t_purstd
t_rstia
Configuration Strap
Pins Input
Configuration Strap
Pins Output Drive
t_css
t_csh
t_otaa
t_odad
TABLE 5-8: POWER-ON nRST & CONFIGURATION STRAP TIMING VALUES
Symbol
t_purstd
t_purstv
t_rstia
t_css
t_csh
t_otaa
t_odad
Description
External power supplies at operational level to nRST
deassertion
External power supplies at operational level to nRST
valid
nRST input assertion time
Configuration strap pins setup to nRST deassertion
Configuration strap pins hold after nRST deassertion
Output tri-state after nRST assertion
Output drive after nRST deassertion
Min.
25
0
100
200
1
2
Typ.
Max.
Unit
ms
ns
µs
ns
ns
50
ns
800
ns
(see Note 1)
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7, "Configuration
Straps" for details. Configuration straps must only be pulled high or low and must not be driven as inputs.
Note 1: 20 clock cycles for 25 MHz, or 40 clock cycles for 50 MHz
DS00001987A-page 118
 2013-2015 Microchip Technology Inc.