LAN8740A Datasheet, PDF (122/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
5.6.4 RMII INTERFACE TIMING
This section specifies the RMII interface transmit and receive timing.
Note:
The CRS_DV pin performs both carrier sense and data valid functions. CRS_DV is asserted asynchro-
nously on detection of carrier due to the criteria relevant to the operating mode. If the PHY has additional
bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device will assert
CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and deassert CRS_DV on
cycles of REF_CLK which present the first di-bit of a nibble. For additional information, refer to the RMII
specification.
FIGURE 5-6:
RMII TIMING
CLKIN
(REF_CLK)
(INPUT)
t_clkp
t_clkh t_clkl
t_oval
t_oval
t_oinvld
RXD[1:0], RXER
(OUTPUTS)
CRS_DV
(OUTPUT)
TXD[1:0]
(INPUTS)
TXEN
(INPUT)
t_oinvld
t_su t_ihold
t_ihold
t_su t_ihold
t_oval
t_ihold
t_su
TABLE 5-12: RMII TIMING VALUES
Symbol
Description
Min.
Typ.
t_clkp
t_clkh
t_clkl
t_oval
t_oinvld
t_su
t_ihold
CLKIN period
CLKIN high time
CLKIN low time
RXD[1:0], RXER, CRS_DV output
valid from rising edge of CLKIN
RXD[1:0], RXER, CRS_DV output
invalid from rising edge of CLKIN
TXD[1:0], TXEN setup time to ris-
ing edge of CLKIN
TXD[1:0], TXEN input hold time
after rising edge of CLKIN
20
t_clkp * 0.35
t_clkp * 0.35
3.0
4.0
1.5
Note 1: Timing was designed for system load between 10 pF and 25 pF.
Max.
t_clkp * 0.65
t_clkp * 0.65
15.0
Unit
Note
ns
ns
ns
ns (see Note 1)
ns (see Note 1)
ns (see Note 1)
ns (see Note 1)
DS00001987A-page 122
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