LAN8740A Datasheet, PDF (34/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.7.2 MODE[2:0]: MODE CONFIGURATION
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-
serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is
then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,
the configuration of the 10/100 digital block is controlled by the register bit values and the MODE[2:0] configuration
straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-6. The user
may configure the transceiver mode by writing the SMI registers.
TABLE 3-6: MODE[2:0] BUS
MODE[2:0]
Mode Definitions
000
10BASE-T Half Duplex. Auto-negotiation disabled.
001
10BASE-T Full Duplex. Auto-negotiation disabled.
010
100BASE-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
011
100BASE-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100
100BASE-TX Half Duplex is advertised. Auto-negoti-
ation enabled.
CRS is active during Transmit & Receive.
101
Repeater mode. Auto-negotiation enabled.
100BASE-TX Half Duplex is advertised.
CRS is active during Receive.
110
Power-Down mode. In this mode the transceiver will
wake-up in Power-Down mode. The transceiver can-
not be used when the MODE[2:0] bits are set to this
mode. To exit this mode, the MODE bits in Register
18.7:5 (see Section 4.2.14, "Special Modes Register")
must be configured to some other value and a soft
reset must be issued.
111
All capable. Auto-negotiation enabled.
Default Register Bit Values
Register 0
Register 4
[13,12,10,8]
0000
0001
1000
[8,7,6,5]
N/A
N/A
N/A
1001
N/A
1100
0100
1100
0100
N/A
N/A
X10X
1111
The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3-7.
TABLE 3-7: PIN NAMES FOR MODE BITS
MODE Bit
MODE[0]
MODE[1]
MODE[2]
Pin Name
RXD0/MODE0
RXD1/MODE1
COL/CRS_DV/MODE2
3.7.3 RMIISEL: MII/RMII MODE CONFIGURATION
MII or RMII mode selection is latched on the rising edge of the internal reset (nRST) based on the strapping of the
RMIISEL configuration strap. The default mode is MII (via the internal pull-down resistor). To select RMII mode, pull the
RMIISEL configuration strap high with an external resistor to VDDIO.
When the nRST pin is deasserted, the MIIMODE bit of the Special Modes Register is loaded according to the RMIISEL
configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes Register.
Refer to Section 3.4, "MAC Interface" for additional information on MII and RMII modes.
DS00001987A-page 34
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