LAN8740A Datasheet, PDF (51/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.8.12 LOOPBACK OPERATION
The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the fol-
lowing subsections.
3.8.12.1 Near-end Loopback
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi-
cated by the blue arrows in Figure 3-14. The near-end loopback mode is enabled by setting the Loopback bit of the
Basic Control Register to “1”. A large percentage of the digital circuitry is operational in near-end loopback mode
because data is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL signal
will be inactive in this mode, unless Collision Test is enabled in the Basic Control Register. The transmitters are powered
down regardless of the state of TXEN. Refer to Section 5.6.3.1, "100 Mbps Internal Loopback MII Timing" for additional
loopback timing information.
FIGURE 3-14:
NEAR-END LOOPBACK BLOCK DIAGRAM
10/100
Ethernet
MAC
TXD
RXD
Digital
X ^TX
X ^RX
Analog
Microchip
Ethernet Transceiver
XFMR
CAT-5
3.8.12.2 Far Loopback
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure 3-15. The far
loopback mode is enabled by setting the FARLOOPBACK bit of the Mode Control/Status Register to “1”. In this mode,
data that is received from the link partner on the MDI is looped back out to the link partner. The digital interface signals
on the local MAC interface are isolated.
Note: This special test mode is only available when operating in RMII mode.
FIGURE 3-15:
FAR LOOPBACK BLOCK DIAGRAM
Far-end system
10/100
Ethernet
MAC
TXD _X
RXD _X
Digital
Analog
Microchip
Ethernet Transceiver
TX
XFMR
RX
CAT-5
Link
Partner
 2013-2015 Microchip Technology Inc.
DS00001987A-page 51