LAN8740A Datasheet, PDF (45/136 Pages) Microchip Technology – Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology

LAN8740A/LAN8740Ai
3.8.7.1 Hardware Reset
A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum
time detailed in Section 5.6.2, "Power-On nRST & Configuration Strap Timing" to ensure a proper transceiver reset.
During a hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.6.2, "Power-On
nRST & Configuration Strap Timing" for additional information.
3.8.7.2 Software Reset
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All registers bits, except
those indicated as “NASR” in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing.
Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5 s from the setting
of this bit.
3.8.8 CARRIER SENSE
The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode. CRS is a signal
defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS based only on receive activity
whenever the transceiver is either in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based
on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier
sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-
secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is
asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after
the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE
followed by some non-IDLE symbol.
3.8.9 COLLISION DETECT
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate
that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously
to both RXCLK and TXCLK. The COL output becomes inactive during full duplex mode.
The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This enables the collision
test. COL will be asserted within 512 bit times of TXEN rising and will be de-asserted within 4 bit times of TXEN falling.
3.8.10 LINK INTEGRITY TEST
The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The
link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the Basic Status Register and to drive
the LINK LED (LED1).
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-
PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is
asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When
received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-
ation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted
until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately
negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic.
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DS00001987A-page 45