PIC18F2450_08 Datasheet, PDF (77/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
REGISTER 6-1: EECON1: MEMORY CONTROL REGISTER 1
U-0
—
bit 7
R/W-x
U-0
R/W-0
R/W-x
R/W-0
CFGS
—
FREE
WRERR⁽¹⁾
WREN
R/S-0
WR
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
CFGS: Flash Program or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3
WRERR: Flash Program Error Flag bit⁽¹⁾
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program
0 = Inhibits write cycles to Flash program
bit 1
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle complete
bit 0
Unimplemented: Read as ‘0’
Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
© 2008 Microchip Technology Inc.
DS39760D-page 75