PIC18F2450_08 Datasheet, PDF (314/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
Code Examples
16 x 16 Signed Multiply Routine ................................ 84
16 x 16 Unsigned Multiply Routine ............................ 84
8 x 8 Signed Multiply Routine .................................... 83
8 x 8 Unsigned Multiply Routine ................................ 83
Changing Between Capture Prescalers ................... 124
Computed GOTO Using an Offset Value ................... 56
Erasing a Flash Program Memory Row ..................... 78
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 67
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ............................... 119
Initializing PORTA ...................................................... 99
Initializing PORTB .................................................... 101
Initializing PORTC .................................................... 104
Initializing PORTD .................................................... 107
Initializing PORTE .................................................... 109
Reading a Flash Program Memory Word .................. 77
Saving STATUS, WREG and
BSR Registers in RAM ....................................... 97
Writing to Flash Program Memory ....................... 80–81
Code Protection ............................................................... 191
COMF ............................................................................... 230
Compare (CCP Module) ................................................... 125
Associated Registers ............................................... 126
CCP1 Pin Configuration ........................................... 125
CCPR1 Register ...................................................... 125
Software Interrupt .................................................... 125
Special Event Trigger ............................................... 125
Timer1 Mode Selection ............................................ 125
Configuration Bits ............................................................. 192
Configuration Register Protection .................................... 211
Context Saving During Interrupts ....................................... 97
Conversion Considerations .............................................. 309
CPFSEQ .......................................................................... 230
CPFSGT ........................................................................... 231
CPFSLT ........................................................................... 231
Crystal Oscillator/Ceramic Resonator ................................ 25
Customer Change Notification Service ............................ 319
Customer Notification Service .......................................... 319
Customer Support ............................................................ 319
D
Data Addressing Modes ..................................................... 67
Comparing Addressing Modes with
the Extended Instruction Set Enabled ................ 71
Direct .......................................................................... 67
Indexed Literal Offset ................................................. 70
BSR Operation ................................................... 72
Instructions Affected .......................................... 70
Mapping the Access Bank ................................. 72
Indirect ....................................................................... 67
Inherent and Literal .................................................... 67
Data Memory ...................................................................... 59
Access Bank .............................................................. 61
and the Extended Instruction Set ............................... 70
Bank Select Register (BSR) ....................................... 59
General Purpose Registers ........................................ 61
Map for PIC18F2450/4450 Devices ........................... 60
Special Function Registers ........................................ 62
Map .................................................................... 62
USB RAM ................................................................... 59
DAW ................................................................................ 232
DC Characteristics ........................................................... 278
Power-Down and Supply Current ............................ 270
Supply Voltage ........................................................ 269
DCFSNZ .......................................................................... 233
DECF ............................................................................... 232
DECFSZ .......................................................................... 233
Dedicated ICD/ICSP Port ................................................ 211
Demonstration, Development and
Evaluation Boards ................................................... 266
Development Support ...................................................... 263
Device Differences ........................................................... 308
Device Overview .................................................................. 7
Features (table) ........................................................... 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Direct Addressing .............................................................. 68
E
Effect on Standard PIC MCU
Instructions .............................................................. 260
Electrical Characteristics ................................................. 267
Enhanced Universal Synchronous Receiver
Transmitter (USART). See EUSART.
Equations
A/D Acquisition Time ............................................... 180
A/D Minimum Charging Time ................................... 180
Calculating the Minimum Required
A/D Acquisition Time ....................................... 180
Errata ................................................................................... 6
EUSART
Asynchronous Mode ................................................ 163
Associated Registers, Receive ........................ 166
Associated Registers, Transmit ....................... 164
Auto-Wake-up on Sync Break ......................... 167
Break Character Sequence ............................. 168
Receiver .......................................................... 165
Receiving a Break Character ........................... 168
Setting Up 9-Bit Mode with
Address Detect ........................................ 165
Transmitter ...................................................... 163
Baud Rate Generator (BRG) ................................... 157
Associated Registers ....................................... 158
Auto-Baud Rate Detect .................................... 161
Baud Rate Error, Calculating ........................... 158
Baud Rates, Asynchronous Modes ................. 159
High Baud Rate Select (BRGH Bit) ................. 157
Operation in Power-Managed Modes .............. 157
Sampling .......................................................... 157
Synchronous Master Mode ...................................... 169
Associated Registers, Receive ........................ 171
Associated Registers, Transmit ....................... 170
Reception ........................................................ 171
Transmission ................................................... 169
Synchronous Slave Mode ........................................ 172
Associated Registers, Receive ........................ 173
Associated Registers, Transmit ....................... 172
Reception ........................................................ 173
Transmission ................................................... 172
DS39760D-page 312
© 2008 Microchip Technology Inc.