PIC18F2450_08 Datasheet, PDF (130/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 13-3:
PWM Resolution (max)
=
log
⎛
⎝
F--F--P^-O--W^{--S---CM---⎠⎞}
-------l--o---g----₍--2---₎-------- bits
13.4.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCP module for PWM operation.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
16
4
1
1
1
1
PR2 Value
FFh
FFh
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
10
10
10
8
7
6.58
TABLE 13-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF
49
RCON
IPEN SBOREN⁽¹⁾
—
RI
TO
PD
POR
BOR
50
PIR1
—
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 51
PIE1
—
ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 51
IPR1
—
ADIP
RCIP
TXIP
—
CCP1IP TMR2IP TMR1IP 51
TRISC
TRISC7 TRISC6
—
—
—
TRISC2 TRISC1 TRISC0 51
TMR2 Timer2 Register
50
PR2
Timer2 Period Register
50
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
CCPR1L Capture/Compare/PWM Register 1 Low Byte
50
CCPR1H Capture/Compare/PWM Register 1 High Byte
50
CCP1CON —
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
DS39760D-page 128
© 2008 Microchip Technology Inc.