PIC18F2450_08 Datasheet, PDF (143/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
14.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an EVEN
transfer and one set for an ODD transfer. This allows
the CPU to process one BD while the SIE is processing
the other BD. Double-buffering BDs in this way allows
for maximum throughput to/from the USB.
The USB module supports three modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the EVEN BD when the module is enabled.
After the completion of a transaction (UOWN cleared
by the SIE), the pointer is toggled to the ODD BD. After
the completion of the next transaction, the pointer is
toggled back to the EVEN BD and so on.
The EVEN/ODD status of the last transaction is stored
in the PPBI bit of the USTAT register. The user can
reset all Ping-Pong Pointers to EVEN using the
PPBRST bit.
Figure 14-7 shows the three different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 14-4. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
FIGURE 14-7:
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
PPB1:PPB0 = 00
No Ping-Pong Buffers
400h
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
47Fh
EP15 IN
Descriptor
PPB1:PPB0 = 01
Ping-Pong Buffer on EP0 OUT
400h
EP0 OUT EVEN
Descriptor
EP0 OUT ODD
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
483h
EP15 IN
Descriptor
PPB1:PPB0 = 10
Ping-Pong Buffers on All EPs
400h
EP0 OUT EVEN
Descriptor
EP0 OUT ODD
Descriptor
EP0 IN EVEN
Descriptor
EP0 IN ODD
Descriptor
EP1 OUT EVEN
Descriptor
EP1 OUT ODD
Descriptor
EP1 IN EVEN
Descriptor
EP1 IN ODD
Descriptor
Available
as
Data RAM
Available
as
Data RAM
4FFh
Maximum Memory Used: 128 bytes
Maximum BDs: 32 (BD0 to BD31)
4FFh
Maximum Memory Used: 132 bytes
Maximum BDs: 33 (BD0 to BD32)
Note: Memory area not shown to scale.
4FFh
EP15 IN ODD
Descriptor
Maximum Memory Used: 256 bytes
Maximum BDs: 64 (BD0 to BD63)
© 2008 Microchip Technology Inc.
DS39760D-page 141