PIC18F2450_08 Datasheet, PDF (76/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Table Pointer⁽¹⁾
TBLPTRU TBLPTRH TBLPTRL
Program Memory
Holding Registers
Program Memory
(TBLPTR)
Table Latch (8-bit)
TABLAT
Note 1:
Table Pointer actually points to one of 16 holding registers, the address of which is determined by
TBLPTRL<3:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
DS39760D-page 74
© 2008 Microchip Technology Inc.