PIC18F2450_08 Datasheet, PDF (66/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on Page:
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
BAUDCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE⁽³⁾
TRISD⁽³⁾
TRISC
TRISB
TRISA
LATE⁽³⁾
LATD⁽³⁾
LATC
LATB
LATA
PORTE
PORTD⁽³⁾
Legend:
Note 1:
2:
3:
4:
5:
6:
IDLEN
—
—
—
OSTS
—
SCS1
SCS0 0--- q-00 50, 31
VDIRMAG
—
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0 0-00 0101 50, 185
—
—
—
IPEN
SBOREN⁽²⁾
—
—
—
—
—
SWDTEN --- ---0 50, 204
RI
TO
PD
POR
BOR
0q-1 11q0 50, 42
Timer1 Register High Byte
xxxx xxxx 50, 120
Timer1 Register Low Byte
xxxx xxxx 50, 120
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 115
Timer2 Register
0000 0000 50, 122
Timer2 Period Register
1111 1111 50, 122
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 121
A/D Result Register High Byte
xxxx xxxx 50, 184
A/D Result Register Low Byte
xxxx xxxx 50, 184
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON --00 0000 50, 175
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 --00 qqqq 50, 176
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 50, 177
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 50, 124
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 50, 124
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 50, 123,
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN 01-0 0-00 51, 156,
EUSART Baud Rate Generator Register High Byte
0000 0000 50, 157
EUSART Baud Rate Generator Register Low Byte
0000 0000 50, 157
EUSART Receive Register
0000 0000 50, 165
EUSART Transmit Register
0000 0000 51, 163
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 51, 154
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 51, 155
Data Memory Control Register 2 (not a physical register)
0000 0000 51, 74
—
CFGS
—
FREE
WRERR
WREN
WR
—
-x-0 x00- 51, 75
OSCFIP
—
USBIP
—
—
HLVDIP
—
—
1-1- -1-- 51, 95
OSCFIF
—
USBIF
—
—
HLVDIF
—
—
0-0- -0-- 51, 91
OSCFIE
—
USBIE
—
—
HLVDIE
—
—
0-0- -0-- 51, 93
—
ADIP
RCIP
TXIP
—
CCP1IP
TMR2IP
TMR1IP -111 -111 51, 94
—
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF -000 -000 51, 90
—
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE -000 -000 51, 92
—
—
—
—
—
TRISE2
TRISE1
TRISE0 ---- -111 51, 110
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 51, 108
TRISC7
TRISC6
—
—
—
TRISC2
TRISC1
TRISC0 11-- -111 51, 106
TRISB7
—
TRISB6
TRISA6⁽⁴⁾
TRISB5
TRISA5
TRISB4
TRISA4
TRISB3
TRISA3
TRISB2
TRISA2
TRISB1
TRISA1
TRISB0
TRISA0
1111 1111 51, 103
-111 1111 51, 100
—
—
—
—
—
LATE2
LATE1
LATE0 ---- -xxx 51, 110
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 51, 108
LATC7
LATC6
—
—
—
LATC2
LATC1
LATC0 xx-- -xxx 51, 106
LATB7
—
—
LATB6
LATA6⁽⁴⁾
—
LATB5
LATA5
—
LATB4
LATA4
—
LATB3
LATA3
RE3⁽⁵⁾
LATB2
LATA2
RE2⁽³⁾
LATB1
LATA1
RE1⁽³⁾
LATB0
LATA0
RE0⁽³⁾
xxxx xxxx
-xxx xxxx
---- x000
51, 103
51, 100
51, 109
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx 51, 108
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
DS39760D-page 64
© 2008 Microchip Technology Inc.