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PIC18F2450_08 Datasheet, PDF (64/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
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PIC18F2450/4450
5.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend
downward to occupy the top segment of Bank 15, from
F60h to FFFh. A list of these registers is given in
Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2450/4450 DEVICES
Address
Name
Address
Name
Address
FFFh
FFEh
FFDh
FFCh
FFBh
TOSU
TOSH
TOSL
STKPTR
PCLATU
FDFh INDF2(1)
FDEh POSTINC2(1)
FDDh POSTDEC2(1)
FDCh PREINC2(1)
FDBh PLUSW2(1)
FBFh
FBEh
FBDh
FBCh
FBBh
FFAh PCLATH
FDAh FSR2H
FBAh
FF9h
PCL
FD9h FSR2L
FB9h
FF8h TBLPTRU
FD8h STATUS
FB8h
FF7h TBLPTRH
FD7h TMR0H
FB7h
FF6h TBLPTRL
FD6h TMR0L
FB6h
FF5h
FF4h
TABLAT
PRODH
FD5h
FD4h
T0CON
—(2)
FB5h
FB4h
FF3h PRODL
FD3h OSCCON
FB3h
FF2h INTCON
FD2h HLVDCON
FB2h
FF1h INTCON2
FD1h WDTCON
FB1h
FF0h INTCON3
FEFh INDF0(1)
FEEh POSTINC0(1)
FEDh POSTDEC0(1)
FECh PREINC0(1)
FEBh PLUSW0(1)
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
FB0h
FAFh
FAEh
FADh
FACh
FABh
FEAh FSR0H
FE9h FSR0L
FE8h WREG
FE7h INDF1(1)
FE6h POSTINC1(1)
FE5h POSTDEC1(1)
FE4h PREINC1(1)
FE3h PLUSW1(1)
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
T2CON
—(2)
—(2)
—(2)
—(2)
—(2)
ADRESH
ADRESL
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FE2h FSR1H
FC2h ADCON0
FA2h
FE1h FSR1L
FC1h ADCON1
FA1h
FE0h
BSR
FC0h ADCON2
FA0h
Name
CCPR1H
CCPR1L
CCP1CON
—(2)
—(2)
—(2)
—(2)
BAUDCON
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—(2)
—(2)
—(2)
EECON2(1)
EECON1
—(2)
—(2)
—(2)
IPR2
PIR2
PIE2
Address
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
Name
IPR1
PIR1
PIE1
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
TRISE(3)
TRISD(3)
TRISC
TRISB
TRISA
—(2)
—(2)
—(2)
—(2)
LATE(3)
LATD(3)
LATC
LATB
LATA
—(2)
—(2)
—(2)
—(2)
PORTE
PORTD(3)
PORTC
PORTB
PORTA
Address
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
Note 1:
2:
3:
Not a physical register.
Unimplemented registers are read as ‘0’.
These registers are implemented only on 40/44-pin devices.
Name
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
UEIR
UIE
UIR
UFRMH
UFRML
—(2)
—(2)
—(2)
—(2)
—(2)
—(2)
DS39760D-page 62
© 2008 Microchip Technology Inc.
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