PIC18F2450_08 Datasheet, PDF (318/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
PRI_IDLE Mode ................................................................. 38
PRI_RUN Mode ................................................................. 34
Program Counter ................................................................ 54
PCL, PCH and PCU Registers ................................... 54
PCLATH and PCLATU Registers .............................. 54
Program Memory
and the Extended Instruction Set ............................... 70
Code Protection ....................................................... 209
Instructions ................................................................. 58
Two-Word .......................................................... 58
Interrupt Vector .......................................................... 53
Look-up Tables .......................................................... 56
Map and Stack (diagram) ........................................... 53
Reset Vector .............................................................. 53
Program Verification and Code Protection ....................... 208
Associated Registers ............................................... 208
Programming, Device Instructions ................................... 213
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 242
PUSH and POP Instructions .............................................. 55
PUSHL ............................................................................. 258
PWM (CCP Module)
Associated Registers ............................................... 128
Duty Cycle ................................................................ 127
Example Frequencies/Resolutions .......................... 128
Period ....................................................................... 127
Setup for PWM Operation ........................................ 128
TMR2 to PR2 Match ................................................ 127
Q
Q Clock ............................................................................ 128
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 39
RC_RUN Mode .................................................................. 36
RCALL .............................................................................. 243
RCON Register
Bit Status During Initialization .................................... 48
Reader Response ............................................................ 320
Register File Summary ................................................. 63–65
Registers
ADCON0 (A/D Control 0) ......................................... 175
ADCON1 (A/D Control 1) ......................................... 176
ADCON2 (A/D Control 2) ......................................... 177
BAUDCON (Baud Rate Control) .............................. 156
BDnSTAT (Buffer Descriptor n Status,
CPU Mode) ...................................................... 139
BDnSTAT (Buffer Descriptor n Status,
SIE Mode) ........................................................ 140
CCP1CON (Capture/Compare/PWM Control) ......... 123
CONFIG1H (Configuration 1 High) .......................... 194
CONFIG1L (Configuration 1 Low) ............................ 193
CONFIG2H (Configuration 2 High) .......................... 196
CONFIG2L (Configuration 2 Low) ............................ 195
CONFIG3H (Configuration 3 High) .......................... 197
CONFIG4L (Configuration 4 Low) ............................ 198
CONFIG5H (Configuration 5 High) .......................... 199
CONFIG5L (Configuration 5 Low) ............................ 199
CONFIG6H (Configuration 6 High) .......................... 200
CONFIG6L (Configuration 6 Low) ............................ 200
CONFIG7H (Configuration 7 High) .......................... 201
CONFIG7L (Configuration 7 Low) ............................ 201
DEVID1 (Device ID 1) .............................................. 202
DEVID2 (Device ID 2) .............................................. 202
EECON1 (Memory Control 1) .................................... 75
DS39760D-page 316
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 185
INTCON (Interrupt Control) ........................................ 87
INTCON2 (Interrupt Control 2) ................................... 88
INTCON3 (Interrupt Control 3) ................................... 89
IPR1 (Peripheral Interrupt Priority 1) ......................... 94
IPR2 (Peripheral Interrupt Priority 2) ......................... 95
OSCCON (Oscillator Control) .................................... 31
PIE1 (Peripheral Interrupt Enable 1) .......................... 92
PIE2 (Peripheral Interrupt Enable 2) .......................... 93
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 90
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 91
PORTE .................................................................... 109
RCON (Reset Control) ......................................... 42, 96
RCSTA (Receive Status and Control) ..................... 155
STATUS .................................................................... 66
STKPTR (Stack Pointer) ............................................ 55
T0CON (Timer0 Control) ......................................... 111
T1CON (Timer1 Control) ......................................... 115
T2CON (Timer2 Control) ......................................... 121
TXSTA (Transmit Status and Control) ..................... 154
UCFG (USB Configuration) ..................................... 132
UCON (USB Control) ............................................... 130
UEIE (USB Error Interrupt Enable) .......................... 148
UEIR (USB Error Interrupt Status) ........................... 147
UEPn (USB Endpoint n Control) .............................. 135
UIE (USB Interrupt Enable) ..................................... 146
UIR (USB Interrupt Status) ...................................... 144
USTAT (USB Status) ............................................... 134
WDTCON (Watchdog Timer Control) ...................... 204
RESET ............................................................................. 243
Reset State of Registers .................................................... 48
Reset Timers ..................................................................... 45
Oscillator Start-up Timer (OST) ................................. 45
PLL Lock Time-out ..................................................... 45
Power-up Timer (PWRT) ........................................... 45
Resets ........................................................................ 41, 191
Brown-out Reset (BOR) ........................................... 191
Oscillator Start-up Timer (OST) ............................... 191
Power-on Reset (POR) ............................................ 191
Power-up Timer (PWRT) ......................................... 191
RETFIE ............................................................................ 244
RETLW ............................................................................ 244
RETURN .......................................................................... 245
Return Address Stack ........................................................ 54
and Associated Registers .......................................... 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 307
RLCF ............................................................................... 245
RLNCF ............................................................................. 246
RRCF ............................................................................... 246
RRNCF ............................................................................ 247
S
SEC_IDLE Mode ............................................................... 38
SEC_RUN Mode ................................................................ 34
SETF ................................................................................ 247
Single-Supply ICSP Programming ................................... 212
SLEEP ............................................................................. 248
Sleep
OSC1 and OSC2 Pin States ...................................... 32
Sleep Mode ........................................................................ 37
Software Simulator (MPLAB SIM) ................................... 264
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 191
Special ICPORT Features ............................................... 211
© 2008 Microchip Technology Inc.