PIC18F2450_08 Datasheet, PDF (67/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2450/4450) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on Page:
PORTC
PORTB
PORTA
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UCFG
UADDR
UCON
USTAT
UEIE
UEIR
UIE
UIR
UFRMH
UFRML
Legend:
Note 1:
2:
3:
4:
5:
6:
RC7
RC6
RC5⁽⁶⁾
RC4⁽⁶⁾
—
RC2
RC1
RC0
xxxx -xxx 51, 106
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx 51, 100
—
RA6⁽⁴⁾
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 51, 100
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 51, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 52, 135
UTEYE UOEMON
—
UPUEN
UTRDIS
FSEN
PPB1
PPB0 00-0 0000 52, 132
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0 -000 0000 52, 136
—
PPBRST
SE0
PKTDIS
USBEN RESUME SUSPND
—
-0x0 000- 52, 130
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
—
-xxx xxx- 52, 134
BTSEE
—
—
BTOEE
DFN8EE CRC16EE CRC5EE
PIDEE 0--0 0000 52, 148
BTSEF
—
—
BTOEF
DFN8EF CRC16EF CRC5EF
PIDEF 0--0 0000 52, 147
—
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE -000 0000 52, 146
—
SOFIF
STALLIF
IDLEIF
TRNIF
ACTVIF
UERRIF
URSTIF -000 0000 52, 144
—
—
—
—
—
FRM10
FRM9
FRM8 ---- -xxx 52, 136
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0 xxxx xxxx 52, 136
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
© 2008 Microchip Technology Inc.
DS39760D-page 65