PIC18F2450_08 Datasheet, PDF (32/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2450/4450
2.4 Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F2450/4450 family includes a feature that allows
the device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F2450/4450 devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator. The particular mode is defined by
the FOSC3:FOSC0 Configuration bits. The details of
these modes are covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F2450/4450 devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all power-
managed modes, is often the time base for functions
such as a Real-Time Clock (RTC). Most often, a
32.768 kHz watch crystal is connected between the
RC0/T1OSO/T1CKI and RC1/T1OSI/UOE pins. Like
the XT and HS Oscillator mode circuits, loading
capacitors are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 11.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator is available as a power-managed mode
clock source. The INTRC source is also used as the
clock source for several special features, such as the
WDT and Fail-Safe Clock Monitor.
2.4.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-1) controls several
aspects of the device clock’s operation, both in full-power
operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the primary
clock (defined by the FOSC3:FOSC0 Configuration bits),
the secondary clock (Timer1 oscillator) and the internal
oscillator. The clock source changes immediately, after
one or more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared on all forms
of Reset.
INTRC always remains the clock source for features
such as the Watchdog Timer and the Fail-Safe Clock
Monitor.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes. In
power-managed modes, only one of these three bits will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator has
just started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable prior to
switching to it as the clock source; other-
wise, a very long delay may occur while
the Timer1 oscillator starts.
2.4.2 OSCILLATOR TRANSITIONS
PIC18F2450/4450 devices contain circuitry to prevent
clock “glitches” when switching between clock sources.
A short pause in the device clock occurs during the
clock switch. The length of this pause is the sum of two
cycles of the old clock source and three to four cycles
of the new clock source. This formula assumes that the
new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
DS39760D-page 30
© 2008 Microchip Technology Inc.