PIC18F2450_08 Datasheet, PDF (319/324 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

Stack Full/Underflow Resets .............................................. 56
STATUS Register .............................................................. 66
SUBFSR .......................................................................... 259
SUBFWB .......................................................................... 248
SUBLW ............................................................................ 249
SUBULNK ........................................................................ 259
SUBWF ............................................................................ 249
SUBWFB .......................................................................... 250
SWAPF ............................................................................ 250
T
T0CON Register
PSA Bit ..................................................................... 113
T0CS Bit ................................................................... 112
T0PS2:T0PS0 Bits ................................................... 113
T0SE Bit ................................................................... 112
Table Pointer Operations (table) ........................................ 76
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 251
TBLWT ............................................................................. 252
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ............................................................ 45
Timer0 .............................................................................. 111
16-Bit Mode Timer Reads and Writes ...................... 112
Associated Registers ............................................... 113
Clock Source Edge Select (T0SE Bit) ...................... 112
Clock Source Select (T0CS Bit) ............................... 112
Operation ................................................................. 112
Overflow Interrupt .................................................... 113
Prescaler .................................................................. 113
Switching Assignment ...................................... 113
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 115
16-Bit Read/Write Mode ........................................... 117
Associated Registers ....................................... 120, 126
Interrupt .................................................................... 118
Operation ................................................................. 116
Oscillator .......................................................... 115, 117
Layout Considerations ..................................... 118
Low-Power Option ........................................... 117
Using Timer1 as a Clock Source ..................... 117
Overflow Interrupt .................................................... 115
Resetting, Using a Special Event
Trigger Output (CCP) ....................................... 118
TMR1H Register ...................................................... 115
TMR1L Register ....................................................... 115
Use as a Real-Time Clock ....................................... 118
Timer2 .............................................................................. 121
Associated Registers ............................................... 122
Interrupt .................................................................... 122
Operation ................................................................. 121
Output ...................................................................... 122
PR2 Register ............................................................ 127
TMR2 to PR2 Match Interrupt .................................. 127
Timing Diagrams
A/D Conversion ........................................................ 293
Asynchronous Reception ......................................... 166
Asynchronous Transmission .................................... 164
Asynchronous Transmission
(Back-to-Back) ................................................. 164
Automatic Baud Rate Calculation ............................ 162
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 167
Auto-Wake-up Bit (WUE) During Sleep ................... 167
BRG Overflow Sequence ......................................... 162
Brown-out Reset (BOR) ........................................... 288
© 2008 Microchip Technology Inc.
PIC18F2450/4450
Capture/Compare/PWM (CCP) ............................... 290
CLKO and I/O .......................................................... 287
Clock/Instruction Cycle .............................................. 57
EUSART Synchronous Receive
(Master/Slave) ................................................. 291
EUSART Synchronous Transmission
(Master/Slave) ................................................. 291
External Clock (All Modes Except PLL) ................... 285
Fail-Safe Clock Monitor ........................................... 207
High/Low-Voltage Detect Characteristics ................ 282
High-Voltage Detect (VDIRMAG = 1) ...................... 188
Low-Voltage Detect (VDIRMAG = 0) ....................... 187
PWM Output ............................................................ 127
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 288
Send Break Character Sequence ............................ 168
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
Synchronous Reception
(Master Mode, SREN) ..................................... 171
Synchronous Transmission ..................................... 169
Synchronous Transmission (Through TXEN) .......... 170
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
Timer0 and Timer1 External Clock .......................... 289
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 205
Transition for Wake From Idle to Run Mode .............. 38
Transition for Wake From Sleep (HSPLL) ................. 37
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
USB Signal .............................................................. 292
Timing Diagrams and Specifications ............................... 285
Capture/Compare/PWM
Requirements (CCP) ....................................... 290
CLKO and I/O Requirements ................................... 287
EUSART Synchronous Receive
Requirements .................................................. 291
EUSART Synchronous Transmission
Requirements .................................................. 291
External Clock Requirements .................................. 285
PLL Clock ................................................................ 286
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 288
Timer0 and Timer1 External Clock
Requirements .................................................. 289
USB Full-Speed Requirements ............................... 292
USB Low-Speed Requirements ............................... 292
Top-of-Stack Access .......................................................... 54
TQFP Packages and Special Features ........................... 211
TSTFSZ ........................................................................... 253
DS39760D-page 317