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MAX14830 Datasheet, PDF (61/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs
MAX14830
Quad Serial UART with 128-Word FIFOs
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W A
REGISTER ADDRESS
A
8 DATA BITS
A
P
FROM MASTER TO STAVE
Figure 22. Write Byte Sequence
FROM SLAVE TO MASTER
BURST WRITE
S
DEVICE SLAVE ADDRESS - W A
REGISTER ADDRESS
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - N
A
P
FROM MASTER TO STAVE
Figure 23. Burst Write Sequence
FROM SLAVE TO MASTER
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START, STOP, and Repeated START Conditions
section). Both SDA and SCL remain high when the bus
is not active.
Single-Byte Write
With this operation the master sends an address and one
or two data bytes to the slave device (Figure 22). The
write byte procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
if the address is valid (NAK if not).
6) The master sends an 8-bit data byte.
7) The slave asserts an ACK on the data line.
8) The master generates a STOP condition.
Burst Write
With this operation the master sends an address and
multiple data bytes to the slave device (Figure 23). The
burst write procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not).
6) The master sends 8 bits of data.
7) The slave asserts an ACK on the data line.
8) Repeat steps 6 and 7 as needed.
9) The master generates a STOP condition.
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