MAX14830 Datasheet, PDF (37/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
STSIntEn—STS Interrupt Enable Register
ADDRESS:
0x07
MODE:
R/W
BIT
7
6
5
4
NAME
—
—
ClockRdyIntEn
—
RESET
0
0
0
0
3
GPI3IntEn
0
2
GPI2IntEn
0
1
GPI1IntEn
0
0
GPI0IntEn
0
Bits 7, 6: No Function
Bit 5: ClkRdyIntEn
Set the ClkRdyIntEn bit high to route the ClockReady status bit to the ISR[2]: STSInt bit. If set low, the STSIntEn[5]
masks the ISR[2] bit from the ClockReady status.
Bit 4: No Function
Bits 3–0: GPI[n]IntEn
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7,
UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15. For example, for UART0: Bit 0 is GPI0IntEn, Bit 1 is GPI1IntEn, Bit
2 is GPI2IntEn, and Bit 3 is GPI3IntEn. See Table 1.
The GPI[n]IntEn bits that are set high route the associated STSInt[3:0]: GPI[n]Int bits to the ISR[2] interrupt. Set the
GPI[n]IntEn bits to 0 to disable the associated GPI[n]Int bits.
Maxim Integrated
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