MAX14830 Datasheet, PDF (34/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
LSR—Line Status Register
ADDRESS:
MODE:
BIT
7
NAME
CTSbit
RESET
X
0x04
R
6
—
0
5
RxNoise
0
4
RxBreak
0
3
FrameErr
0
2
RxParityErr
0
1
RxOverrun
0
0
RTimeout
0
The Line Status Register shows all errors related to the word in the RxFIFO most recently read out of the RHR. The LSR
bits are not cleared upon a read; these bits stay set until the next character without errors is read out of the RHR. The
LSR also reflects the current state of the CTS_ input.
Bit 7: CTSbit
The CTSbit reflects the current logic state of the CTS_ input. This bit is cleared when the CTS_ input is low. Following
a power-up or reset, the logic state of CTSbit depends on the input of the CTS_ input.
Bit 6: No Function
Bit 5: RxNoise
If noise is detected on the RX_ input during reception of a character, the RxNoise bit is set for that character. The
RxNoise bit indicates that there was noise on the line while the most recently read character residing in the RHR was
being received. The RxNoise flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[5].
Bit 4: RxBreak
If a line BREAK (RX_ input low for a period longer than the programmed character duration) is detected, a BREAK char-
acter is put in the RxFIFO and the RxBreak bit is set for this character. A BREAK character is represented by an all-zeros
data character. The RxBreak bit distinguishes a regular character with all zeros from a BREAK character. LSR[4] corre-
sponds to the character most recently read out of the RHR. RxBreak is cleared after the character following the BREAK
character is read out of the RHR. The RxBreak flag can generate an ISR[0] interrupt if enabled through LSRIntEn[4].
Bit 3: FrameErr
The FrameErr bit is set high when the received data frame does not match the expected frame format in length. LSR[3]
corresponds to the frame error of the character most recently read out of the RHR. A frame error is related to errors in
expected STOP bits. The FrameErr flag can generate an ISR[0] interrupt, if enabled, through LSRIntEn[3].
Bit 2: RxParityErr
If the parity computed on the character being received does not match the received character’s parity bit, the
RxParityErr bit is set for that character. LSR[2] indicates a parity error for the character most recently read out of the
RHR. In 9-bit multidrop mode (MODE2[6] = 1) the receiver does not check parity and the LSR[2] represents the 9th
(i.e. address or data) bit.
The RxParityErr flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[2].
Bit 1: RxOverrun
If the Receive FIFO is full and additional data is received that does not fit into the Receive FIFO, the LSR[1] bit is set.
The Receive FIFO retains the data in it and discards all new data that does not fit into it. The RxOverrun flag can gener-
ate an ISR[0] interrupt, if enabled through LSRIntEn[1].
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Maxim Integrated