MAX14830 Datasheet, PDF (56/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
SynchDelay1—Synchronization Delay Register 1
ADDRESS:
MODE:
BIT
7
NAME SDelay7
RESET
0
0x21
R/W
6
SDelay6
0
5
SDelay5
0
4
SDelay4
0
3
SDelay3
0
2
SDelay2
0
1
SDelay1
0
0
SDelay0
0
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelay[n]
SDelay[7:0] are the 8 LSBs of the delay between when the UART receives an assigned transmitter trigger command
and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate). The
maximum delay is 65,535-bit intervals.
For example, given a baud rate of 230.4kbps and a bit time of 4.34Fs, the maximum delay is 284ms.
SynchDelay2—Synchronization Delay Register 2
ADDRESS:
MODE:
BIT
7
NAME SDelay15
RESET
0
0x22
R/W
6
SDelay14
0
5
SDelay13
0
4
SDelay12
0
3
SDelay11
0
2
SDelay10
0
1
SDelay9
0
0
SDelay8
0
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelay[n]
SDelay[15:8] are the 8 MSBs of the delay between when the UART receives an assigned transmitter trigger command
and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate). The
maximum delay is 65,535-bit intervals.
For example, given a baud rate of 230.4kbps and a bit time of 4.34Fs, the maximum delay is 284ms.
TIMER1—Timer Register 1
ADDRESS:
MODE:
BIT
NAME
RESET
7
Timer7
0
0x23
R/W
6
Timer6
0
5
Timer5
0
4
Timer4
0
3
Timer3
0
2
Timer2
0
1
Timer1
0
0
Timer0
0
The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output.
The low-frequency clock is a divided replica of the fractional divider output.
Bits 7–0: Timer[n]
Timer[7:0] are the 8 LSBs of the 15-bit timer divisor. See the TIMER2 register description.
If TIMER1 and TIMER2 are both 0x00, the low-frequency clock is off.
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Maxim Integrated