MAX14830 Datasheet, PDF (28/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
register to determine which UART is the source of the
interrupt. The interrupt sources are divided into top-level
and low-level interrupts. The top-level interrupts typically
occur more often and can be read out directly through
the ISR. The low-level interrupts typically occur less often
and their specific source can be read out through the
LSR, STSInt, or SpclChar registers. The three LSBs of the
ISR point to the low-level interrupt registers that contain
the detail of the interrupt source.
Interrupt Enabling
Every interrupt bit of the four interrupt registers can be
enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn, and STSIntEn registers.
Interrupt Clearing
When an ISR interrupt is pending (i.e. any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers are also clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
Reading the GlobalIRQ register does not clear the IRQ
interrupt.
Register Map
(All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
REGISTER
ADDR
FIFO DATA
RHR†
THR†
0x00
0x00
INTERRUPTS
IRQEn
ISR*†
0x01
0x02
LSRIntEn
LSR*†
0x03
0x04
SpclChrIntEn
SpclCharInt†
STSIntEn¥
STSInt†¥
0x05
0x06
0x07
0x08
UART MODES
MODE1
0x09
MODE2
0x0A
LCR*
0x0B
RxTimeOut
0x0C
HDplxDelay
0x0D
IrDA
0x0E
FIFOs CONTROL
FlowLvl
0x0F
FIFOTrgLvl*
TxFIFOLvl†
RxFIFOLvl†
0x10
0x11
0x12
FLOW CONTROL
FlowCtrl
0x13
XON1
0x14
XON2
0x15
XOFF1
0x16
XOFF2
0x17
BIT7
RData7
TData7
CTSIEn
CTSInt
—
CTSbit
—
—
—
—
IRQSel
EchoSuprs
RTSbit
TimOut7
Setup3
—
Resume3
RxTrig3
TxFL7
RxFL7
SwFlow3
Bit7
Bit7
Bit7
Bit7
BIT6
BIT5
BIT4
RData6
TData6
RData5
TData5
RData4
TData4
RFifoEmtyIEn
RFifoEmptyInt
—
—
—
—
—
—
TFifoEmtyIEn
TFifoEmptyInt
RxNoiseIntEn
RxNoise
MltDrpIntEn
MultiDropInt
ClockRdyIntEn
ClockReady
TFifoTrgIEn
TFifoTrigInt
RBreakIEn
RxBreak
BREAKIntEn
BREAKInt
—
—
—
MultiDrop
TxBreak
TimOut6
Setup2
—
—
LoopBack
ForceParity
TimOut5
Setup1
TxInv
TrnscvCtrl
SpecialChr
EvenParity
TimOut4
Setup0
RxInv
Resume2
RxTrig2
TxFL6
RxFL6
Resume1
RxTrig1
TxFL5
RxFL5
Resume0
RxTrig0
TxFL4
RxFL4
SwFlow2
Bit6
Bi6
Bit6
Bi6
SwFlow1
Bit5
Bit5
Bit5
Bit5
SwFlow0
Bit4
Bit4
Bit4
Bit4
BIT3
RData3
TData3
RFifoTrgIEn
RFifoTrigInt
FrameErrIEn
FrameErr
XOFF2IntEn
XOFF2Int
GPI3IntEn
GPI3Int
RTSHiZ
RxEmtyInv
ParityEn
TimOut3
Hold3
MIR
Halt3
TxTrig3
TxFL3
RxFL3
SwFlowEn
Bit3
Bit3
Bit3
Bit3
BIT2
RData2
TData2
STSIEn
STSInt
ParityIEn
RxParityErr
XOFF1IntEn
XOFF1Int
GPI2IntEn
GPI2Int
TXHiZ
RxTrgInv
StopBits
TimOut2
Hold2
RTSInvert
Halt2
TxTrig2
TxFL2
RxFL2
GPIAddr
Bit2
Bit2
Bit2
Bit2
BIT1
RData1
TData1
SpclChrIEn
SpCharInt
ROverrIEn
RxOverrun
XON2IntEn
XON2Int
GPI1IntEn
GPI1Int
TxDisabl
FIFORst
Length1
TimOut1
Hold1
SIR
Halt1
TxTrig1
TxFL1
RxFL1
AutoCTS
Bit1
Bit1
Bit1
Bit1
BIT0
RData0
TData0
LSRErrIEn
LSRErrInt
RTimoutIEn
RTimeout
XON1IntEn
XON1Int
GPI0IntEn
GPI0Int
RxDisabl
RST
Length0
TimOut0
Hold0
IrDAEn
Halt0
TxTrig0
TxFL0
RxFL0
AutoRTS
Bit0
Bit0
Bit0
Bit0
28  
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