MAX14830 Datasheet, PDF (22/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
UART_
TmrtoGPIO
fREF
FRACTIONAL
RATE
DIVIDE-BY-1024
TIMERx
GENERATOR
GPIO_
GPIO_
Figure 9. GPIO_ Clock Pulse Generator
Low-Frequency Timer
The general-purpose timer can be used to generate a
low-frequency clock at a GPIO output and can, for exam-
ple, be used to drive external LEDs. The low-frequency
clock is a divided replica of a given UART baud-rate
clock. The timer is internally routed to the GPIO_ outputs
when enabled in the TIMER2 register as follows:
•UART0: GPIO1
•UART1: GPIO5
•UART2: GPIO9
•UART3: GPIO13
The clock pulses at the GPIOs are generated at a rate
defined by the baud-rate generator and the timer divider
(Figure 9). The baud-rate generator clock is divided by
(1024 x TIMERx), where TIMERx is a 15-bit integer pro-
grammed into the TIMER1 and TIMER2 registers. The
timer output is a 50% duty cycle clock.
UART Clock to GPIO
The MAX14830 reference clock can be routed to the
GPIO0, GPIO4, GPIO8, and/or GPIO12 outputs in case a
synchronous high-frequency clock is needed by another
device. Enable routing a UART clock to GPIO0, GPIO4,
GPIO8, and/or GPIO12 in the TxSynch register. This out-
put clock could, for example, be used to clock another
UART device (Figure 29).
Multidrop Mode
In Multidrop Mode, also known as 9-bit mode, the word
length is 8 bits and a 9th bit is used for distinguishing
between an address and a data word. Multidrop mode is
enabled through MODE2[6]: MultiDrop. Parity checking
is disabled and an SpclCharInt[5]: MultiDropInt interrupt
is generated when an address (9th bit set) is received.
It is up to the host processor to filter out the data intended
for its address. Alternatively the auto data filtering mode
can be used to automatically filter out the data intended
for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop Mode
In multidrop mode, the MAX14830 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
value and GPIO hardware inputs. Use either XOFF2 or
XOFF2[7:4] in combination with GPIO_ to define the
address.
Enable multidrop mode by setting MODE2[6]: MultiDrop
to 1 and enable auto data filtering by setting MODE2[4]:
SpecialChr to 1.
When using register bits in combination with GPIO_ to
define the address, the MSB of the address is written to
XOFF2[7:4] register bits, while the LSBs of the address
are defined through the GPIOs. To enable this mode,
set FlowCtrl[2]: GPIAddr, MODE2[4]: SpecialChr, and
MODE2[6]: MultiDrop to 1. GPIO_ are automatically read
when FlowCtrl[2]: GPIAddr is set to 1, and the address
is updated on logic changes at GPIO_.
In the auto data filtering mode, the MAX14830 auto-
matically accepts data that is meant for its address and
places this into the Receive FIFO, while it discards data
that is not meant for its address. The received address
word is not put into the FIFO.
Auto Transceiver Direction Control
In some half-duplex communication systems the trans-
ceiver’s transmitter must be turned off when data is
being received so as not to load the bus. This is the
case in half-duplex RS-485 communication. Similarly
in full-duplex multidrop communication, like RS-485
or RS-422/V.11, only one transmitter can be enabled
at any one time and the others must be disabled. The
MAX14830 can automatically enable/disable a trans-
ceiver’s transmitter and/or receiver. This relieves the host
processor of this time-critical task.
The RTS_ output is used to control the transceivers’
transmit enable input and is automatically set high
when the MAX14830’s transmitter starts transmission.
22  
Maxim Integrated