MAX14830 Datasheet, PDF (40/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
MODE2 Register
ADDRESS:
MODE:
BIT
7
NAME EchoSuprs
RESET
0
0x0A
R/W
6
MultiDrop
0
5
Loopback
0
4
SpecialChr
0
3
RxEmtyInv
0
2
RxTrigInv
0
1
0
FIFORst RST
0
0
Bit 7: EchoSuprs
Set the EchoSuprs bit high so that the receiver (RX_) gates any data it receives when its transmitter is busy transmitting. In
half-duplex communication (like IrDA and RS-485) this allows blocking of the locally echoed data. The receiver can block
data for an extended time after the transmitter ceases transmission by programming a hold time in HDplxDelay[3:0] bits.
Bit 6: MultiDrop
Set the MultiDrop bit high to enable the 9-bit multidrop mode. If this bit is set, parity checking is not performed by the
receiver and parity generation is not done by the transmitter. The parity error bit, LSR[2], has a different meaning in
this case. The parity error bit represents the 9th bit (address/data indication) that is received with each 9-bit character.
Bit 5: Loopback
Set the Loopback bit high to enable internal local loopback mode. This internally connects TX_ to RX_ and also RTS_ to CTS_.
In local loopback mode, the TX_ output and the RX_ input are disconnected from the internal transmitter and receiver. The
TX_ output is in three-state. The RTS_ output remains connected to the internal logic and reflects the logic state programmed
in LCR[7]. The CTS_ input is disconnected from RTS_ and the internal logic. CTS_ thus remains in a high-impedance state.
Bit 4: SpecialChr
The SpecialChr bit enables special character detection. The receiver can detect up to four special characters, as
selected in FlowCtrl[5:4] and defined in the XON1, XON2, XOFF1 and/or XOFF2 registers, possibly in combination with
GPIO_ inputs, enabled through FlowCtrl[2]: GPIAddr. When a special character is received it is put into the RxFIFO
and a special character detect interrupt ISR[1] is generated.
Special character detection can be used in addition to auto XON/XOFF flow control, if enabled through FlowCtrl[3]. In
this case XON/XOFF flow control is then limited to single character XON and XOFF and only two special characters
can then be defined (in XON2 and XOFF2).
Bit 3: RxEmtyInv
The RxEmtyInv bit inverts the meaning of the receiver empty interrupt: ISR[6]: RFifoEmptyInt. If RxEmtyInv is set low
(default state), the ISR[6] interrupt is generated when the last character residing in the Receive FIFO is read out of the
RHR, and the Receive FIFO becomes empty. If the RxEmtyInv is set high, the ISR[6] interrupt is generated when the
Receive FIFO is empty, and the UART receives at least one character.
Bit 2: RxTrigInv
The RxTrigInv bit inverts the meaning of the RxFIFO triggering. When set, an ISR[3]: RFifoTrigInt is generated when
the RxFIFO is emptied to the trigger level: FIFOTrgLvl[7:4]. If the RxTrgInv bit is low (default state), the ISR[3] interrupt
is generated when the RxFIFO fill level, which starts from a level below FIFOTrgLvl[7:4], is filled up to the trigger level
programmed into FIFOTrgLvl[7:4].
Bit 1: FIFORst
Set the FIFORst bit high to clear both the Receive and Transmit FIFOs of all data contents. After the FIFO reset, the
FIFORst bit must then be set back to 0 to continue normal operation.
40  
Maxim Integrated