MAX14830 Datasheet, PDF (42/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
RxTimeOut—Receiver Timeout Register
ADDRESS:
MODE:
BIT
7
NAME TimOut7
RESET
0
0x0C
R/W
6
TimOut6
0
5
TimOut5
0
4
TimOut4
0
3
TimOut3
0
2
TimOut2
0
1
TimOut1
0
0
TimOut0
0
Bits 7–0: TimOut[n]
The receive data timeout bits allow programming a time delay after the last (newest) character in the Receive FIFO was
received until a receive data timeout LSR[0] interrupt is generated. The duration is measured in character intervals and
is dependent on the character length, parity, and STOP bit setting and is inversely proportional to the baud rate. If the
RxTimeOut value equals zero, a timeout interrupt is not generated.
HDplxDelay Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
Setup3
0
0x0D
R/W
6
Setup2
0
5
Setup1
0
4
Setup0
0
3
Hold3
0
2
Hold2
0
1
Hold1
0
0
Hold0
0
The HDplxDelay register allows programming setup and hold times between RTS_ and the TX_ output in automatic
transceiver direction control mode (MODE1[4] = 1). The Hold[3:0] time can also be used for echo suppression in half-
duplex communication. HDplxDelay also functions in the 2x and 4x rate modes.
Bits 7–4: Setup[n]
The Setup[n] bits define a setup time for RTS_ to transition high before the transmitter starts transmission of its first
character in auto transceiver direction control mode: MODE1[4]. This allows the MAX14830 to account for skew differ-
ences of the external transmitter’s enable delay and propagation delays. Setup[n] bits can also be used to fix a stable
state on the transmission line prior to start of transmission.
The unit of the HDplxDelay setup time delay is one bit interval, making this delay baud-rate dependent. The maximum
delay is 15-bit intervals.
Bits 3–0: Hold[n]
The Hold[n] bits define a hold time for RTS_ to be held stable (high) after the transmitter ends transmission of its last
character in auto transceiver direction control mode: MODE1[4]. RTS_ turns low after the last STOP bit was sent with
a Hold[n] delay. This keeps the external transmitter enabled during the Hold duration.
The second factor that the Hold[n] bits define is a delay in echo suppression mode, MODE2[7]. See the Echo
Suppression section for more information.
The unit of the HDplxDelay hold time delay is one bit interval, making the delay baud-rate dependent. The maximum
delay is 15-bit intervals.
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Maxim Integrated