MAX14830 Datasheet, PDF (27/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Transmitter Flow Control
When auto transmitter control (FlowCtrl[5:4]) is enabled,
the receiver compares all received words with the XOFF
and XON characters. If an XOFF character is received,
the MAX14830 halts its transmitter from sending further
data. The receiver is not affected and continues reception.
Upon receiving XON, the transmitter then restarts sending
data. The received XON and XOFF characters are filtered
out and are not put into the Receive FIFO, as they do not
have significance to the higher layer protocol. An inerrupt
is not generated.
Turn the transmitter off (MODE1[1] = 1) before enabling
transmitter control.
Receiver Overflow Control
When auto receiver overflow control (FlowCtrl[7:6]) is
enabled, the MAX14830 automatically sends XOFF and
XON control characters to the far end UART to avoid
receiver overflow. XOFF1/XOFF2 is/are sent when the
Receive FIFO fill level reaches the HALT value set in the
FlowLvl register. When the host controller reads data
from the Receive FIFO to a level equal to the RESUME
level programmed into the FlowLvl register, XON1/XON2
is/are automatically sent to the far end station to signal it
to resume data transmission.
XON1/XOFF1 is transmitted before XON2/XOFF2 when
dual character (XON1 and XON2/XOFF1 and XOFF2)
flow control is enabled.
Power-Up and IRQ
IRQ has two functions. During normal operation
(MODE1[7] = 1), IRQ operates as a hardware interrupt
output, whereby the IRQ is active when an interrupt is
pending. An IRQ interrupt can only be produced during
normal operation if at least one of the IRQEn interrupt
enable bits are enabled.
During power-up or following a reset, IRQ has a different
function. It is held low until the MAX14830 is ready for
programming following an initialization delay. Once IRQ
goes high, the MAX14830 is ready to be programmed.
The MODE1[7]: IRQSel bit should then be set to enable
normal IRQ interrupt operation.
In polled mode, the DIVLSB register can be polled to
check whether the MAX14830 is ready for operation. If
the controller gets a valid response from DIVLSB, then
the MAX14830 is ready for operation.
Shutdown Mode
Pull RST to DGND to enter shutdown mode. Shutdown
mode is the lowest power consumption mode. In shut-
down mode, all of the MAX14830 circuitry is off. This
includes the SPI/I²C interface, the registers, the FIFOs,
and clocking circuitry. The LDO is on in shutdown mode.
When the RST input is high, the MAX14830 exits shut-
down mode. The chip initialization is completed when the
MAX14830 sets IRQ to logic-high.
The MAX14830 needs to be reprogrammed following a
shutdown.
Interrupt Structure
The structure of the interrupt is shown in Figure 16.
There are four interrupt source registers for each UART:
ISR, LSR, STSInt, and SpclCharInt. Read the GlobalIRQ
POWER-UP
COMPLETED
[4]
MODE1[7]:IRQSEL
IRQ
4
[0]
ISR
7654 3210
GlobalIRQ
0 0 0 0 IRQ3 IRQ2 IRQ1 IRQ0
8
8
8
8
ISR
ISR
76543210 76543210
ISR
7 65 432 10
8
LOW-LEVEL INTERRUPTS ⁸
STSInt
76 54 3210
SpclCharInt
76 5 432
TOP-LEVEL
INTERRUPTS
10
7
65
8
LSR
432
10
Figure 16. Simplified Interrupt Structure
Maxim Integrated
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