MAX14830 Datasheet, PDF (32/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
ISR—Interrupt Status Register
ADDRESS:
MODE:
BIT
7
NAME CTSInt
RESET
0
0x02
COR
6
RFifoEmptyInt
1
5
TFifoEmptyInt
1
4
TFifoTrigInt
0
3
RFifoTrigInt
0
2
STSInt
0
1
SpCharInt
0
0
LSRErrInt
0
The Interrupt Status Register provides an overview of all interrupts generated in the MAX14830. These interrupts are
cleared upon reading the ISR. When the MAX14830 is operated in polled mode, the ISR can be polled to establish
the UART’s status. In interrupt-driven mode, IRQ interrupts are enabled through the appropriate IRQEn bits. The ISR
contents give direct information on the cause for the interrupt or point to other registers that contain more detailed
information.
Bit 7: CTSInt
The CTSInt is set when a logic state transition occurs at the CTS_ input. This bit is cleared after ISR is read. The current
logic state of the CTS_ input can be read out through LSR[7]: CTS bit.
Bit 6: RFifoEmptyInt
The RFifoEmptyInt is set when the Receive FIFO is empty. This bit is cleared after ISR is read. Its meaning can be
inverted by setting the MODE2[3]: RxEmtyInt bit.
Bit 5: TFifoEmptyInt
The TFifoEmptyInt bit is set when the Transmit FIFO is empty. This bit is cleared once ISR is read.
Bit 4: TFifoTrigInt
The TFifoTrigInt bit is set when the number of characters in the Transmit FIFO is equal to or greater than the Transmit
FIFO trigger level defined in FIFOTrigLvl[3:0]. TFifoTrigInt is cleared when the Transmit FIFO level falls below the trigger
level or after the ISR is read. It can be used as a warning that the Transmit FIFO is nearing overflow.
Bit 3: RFifoTrigInt
The RFifoTrigInt bit is set when the Receive FIFO fill level reaches the Receive FIFO trigger level, as defined in
FIFOTrigLvl[7:4]. This can be used as an indication that the Receive FIFO is nearing overrun. It can also be used to
report that a known number of words are available that can be read out in one block. The meaning of RFifoTrigInt can
be inverted through MODE2[2]. RFifoTrigInt is cleared when ISR is read.
Bit 2: STSInt
The STSInt bit is set high when any bit in the STSInt register that is enabled through a STSIntEn bit is high. The STSInt
bit is cleared upon reading ISR.
Bit 1: SpCharInt
The SpCharInt bit is set high when a special character is received, a line BREAK is detected or an address character is
received in multidrop mode. The cause for the SpCharInt interrupt can be read from the SpclCharInt register, if enabled
through the SpclChrIntEn bits. The SpCharInt interrupt is cleared when the ISR is read.
Bit 0: LSRErrInt
The LSRErrInt bit is set high when any LSR bits, which are enabled through the LSRIntEn, are set. This bit is cleared
after the ISR is read.
32  
Maxim Integrated