MAX14830 Datasheet, PDF (59/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
CS
SCLK
MOSI
R U1 U0 A4 A3 A2 A1 A0
X
HiZ
MISO
IRQ3 IRQ2 IRQ1 IRQ0 D7 D6 D5 D4 D3 D2 D1 D0
UX = UART ADDRESS
AX = REGISTER ADDRESS
DX = EIGHT-BIT REGISTER CONTENTS
= INSTANT AT WHICH MAX14830 SAMPLES MOSI DATA
= INSTANT AT WHICH MAX14830 WRITES MISO DATA
Figure 19. SPI Read Cycle
CS
SCLK
MOSI
R
U1
U0
A4
A3
A2
A1
A0
HiZ
MISO
IRQ3
IRQ2
IRQ1
IRQ0
UX = UART ADDRESS
AX = REGISTER ADDRESS
= INSTANT AT WHICH MAX14830 SAMPLES MOSI DATA
= INSTANT AT WHICH MAX14830 WRITES MISO DATA
Figure 20. SPI Fast Read Cycle
Fast Read Cycle
On the MAX14830 the four UART interrupts share the
single IRQ output. When operating in interrupt-based
mode, the microcontroller needs to locate the source of
the interrupt (i.e. which of the four UARTs generated the
interrupt) and clear the interrupt.
To locate the source of an interrupt more quickly, the
MAX14830 implements the SPI fast read cycle. This
means that the microcontroller can determine which
UART is the source of the interrupt (UART0, UART1,
UART2, or UART3) using only 8 clock cycles (Figure 20).
U1 and U0 bits are ignored during the fast read cycle.
Maxim Integrated
I²C Interface
The MAX14830 contains an I²C-compatible interface
for data communication with a host processor (SCL and
SDA). The interface supports a clock frequency up to
1MHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
START, STOP, and Repeated START Conditions
When writing to the MAX14830 using I²C, the master
sends a START condition (S) followed by the MAX14830
I²C address. After the address, the master sends
the register address of the register that is to be pro-
grammed. The master then ends communication by
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