MAX14830 Datasheet, PDF (30/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
The MAX14830 has registers that are 8 bits wide.
RHR—Receive Hold Register
ADDRESS:
MODE:
BIT
NAME
RESET
7
RData7
X
0x00
R
6
RData6
X
5
RData5
X
4
RData4
X
Detailed Register Description
3
RData3
X
2
RData2
X
1
RData1
X
0
RData0
X
Bits 7­–0: RData[n]
The RHR is the bottom of the Receive FIFO and is the register used for reading data out of the Receive FIFO. It contains
the oldest (first received) character in the Receive FIFO. RHR[0] is the LSB of the character received at the RX_ input.
It is the first data bit of the serial-data word received by the receiver.
THR—Transmit Hold Register
ADDRESS:
MODE:
BIT
NAME
7
TData7
0x00
W
6
TData6
5
TData5
4
TData4
3
TData3
2
TData 2
1
TData1
0
TData0
Bits 7–0: TData[n]
The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited
in the Transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right
after the START bit.
30  
Maxim Integrated