MAX14830 Datasheet, PDF (38/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
STSInt—Status Interrupt Register
ADDRESS:
0x08
MODE:
R/COR
BIT
7
6
5
4
NAME
—
—
ClockReady
—
RESET
0
0
0
0
3
GPI3Int
0
2
GPI2Int
0
1
GPI1Int
0
0
GPI0Int
0
Bits 7, 6: No Function
Bit 5: ClockReady
The ClockReady bit is set high when the clock, the divider, and PLL have settled and the MAX14830 is ready for
data communication. The ClockReady bit only works with the crystal oscillator. It does not work with external clocking
through XIN.
The ClockReady status bit is cleared when the clock is disabled and is not cleared upon read. This bit can generate
an ISR[2]: STSInt interrupt, if enabled through STSIntEn[5].
Bit 4: No Function
Bits 3–0: GPI[n]Int
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7,
UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15. For example, for UART0: Bit 0 is GPI0Int, Bit 1 is GPI1Int, Bit 2 is
GPI2Int, and Bit 3 is GPI3Int. See Table 1.
The GPI[n]Int interrupts are set high when a change of logic state occurs on the associated GPIO_ input, unless
disabled by the GPI[n]IntEn bits. GPI[n]Int is cleared upon reading. These interrupts can be selectively routed to the
ISR[2] interrupt bit through the STSIntEn[3:0].
Table 1. UART GPIO Assignments for GPIO Interrupts
UART
UART0
UART1
UART2
UART3
GPI3Int/GPI3IntEn
GPIO3
GPIO7
GPIO11
GPIO15
GPI2Int/GPI2IntEn
GPIO2
GPIO6
GPIO10
GPIO14
GPI1Int/GPI1IntEn
GPIO1
GPIO5
GPIO9
GPIO13
GPI0Int/GPI0IntEn
GPIO0
GPIO4
GPIO8
GPIO12
38  
Maxim Integrated