MAX14830 Datasheet, PDF (43/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
IrDA Register
ADDRESS:
MODE:
BIT
7
NAME
—
RESET
0
0x0E
R/W
6
—
0
5
TxInv
0
4
RxInv
0
3
2
1
MIR
RTSInvert
SIR
0
0
0
0
IrDAEn
0
The IrDA register allows selection of IrDA SIR- and MIR-compliant pulse shaping at the TX_ and RX_ interfaces. It also
allows inversion of the TX_ and RX_ logic, independently of whether IrDA is enabled or not.
Bits 7, 6: No Function
Bit 5: TxInv
Set the TxInv bit high to invert the logic at the TX_ output. This is independent of IrDA operation.
Bit 4: RxInv
Set the RxInv bit high to invert the logic state at the RX_ input. This is independent of IrDA operation.
Bit 3: MIR
Set the MIR and IrDAEn bits high to select IrDA 1.1 (MIR) with 1/4 period pulse widths.
Bit 2: RTSInvert
Set the RTSInvert bit high to invert the RTS output.
Bit 1: SIR
Set the SIR bit and the IrDAEn bits high to select IrDA 1.0 pulses (SIR) with 3/16th period pulses.
Bit 0: IrDAEn
Set the IrDAEn bit high so that IrDA compliant pulses are produced at the TX_ output and the MAX14830 receiver
expects such pulses at its Rx input. If IrDA[0] is set to low (default), normal (non-IrDA) pulses are generated and
expected at the receiver. IrDAEn must be used in conjunction with the SIR, ShortIR, or MIR select bits.
Maxim Integrated
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