MAX14830 Datasheet, PDF (58/68 Pages) Maxim Integrated Products – Quad Serial UART with 128-Word FIFOs

MAX14830
Quad Serial UART with 128-Word FIFOs
Table 10. SPI Command Byte Configuration
BIT 7
W/R
BIT 6
U1
A[4:0] = Register Address
BIT 5
U0
SPI COMMAND BYTE
BIT 4
BIT 3
A4
A3
BIT 2
A2
BIT 1
A1
BIT 0
A0
Table 11. SPI U1, U0 UART Selection
U1
U0
0
0
0
1
1
0
1
1
UART SELECTED
UART0
UART1
UART2
UART3
Serial Controller Interface
The MAX14830 can be controlled through SPI or I²C as
defined by the logic on SPI/I2C. See the Pin Configuration
section for further details.
SPI Interface
The SPI interface supports both single cycle and burst
read/write access. The SPI master must generate clock
and data signals in SPI MODE0 (i.e. with clock polarity
CPOL = 0 and clock phase CPHA = 0).
Each of the four UARTs is addressed using 2 bits (U1
and U0) in the command byte (see Tables 10 and 11).
MISO Operation
Before a specific UART has been addressed, all four
UARTs can attempt to drive MISO. To avoid this conten-
tion, the MISO line is held in high impedance during a
write cycle (Figure 18).
During a read cycle, MISO is high impedance for the
first 4 clock cycles of the command byte. Once the SPI
address (U1 and U0) has been properly decoded, the
addressed SPI drives the MISO line (Figure 19).
SPI Burst Access
Burst access allows writing and reading in one block,
by only defining the initial register address in the SPI
command byte. Multiple characters can be loaded into
the TxFIFO by using the THR (0x00) as the initial burst
write address. Similarly, multiple characters can be read
out of the RxFIFO by using the RHR (0x00) as the SPI’s
burst read address. If the SPI burst address is differ-
ent to 0x00, the MAX14830 automatically increments
the register address after each SPI data byte. Efficient
programming of multiple consecutive registers is thus
possible. Chip select, CS/A0, must be kept low during
the whole cycle. The SCLK/SCL clock continues clocking
throughout the burst access cycle. The burst cycle ends
when the SPI master pulls CS/A0 high.
For example, writing 128 bytes into a TxFIFO can be
achieved by a burst write access through the following
sequence:
1) Pull CS/A0 low.
2) Send SPI write command.
3) Send 128 bytes.
4) Release CS/A0.
This takes a total of (1 + 128) x 8 clock cycles.
CS
SCLK
MOSI X
W U1 U0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
X
HiZ
MISO
AX = REGISTER ADDRESS
UX = UART ADDRESS
DX = EIGHT-BIT REGISTER CONTENTS
= INSTANT AT WHICH MAX14830 SAMPLES MOSI DATA
Figure 18. SPI Write Cycle
58  
Maxim Integrated