MV78100 Datasheet, PDF (97/124 Pages) –

Electrical Specifications
9.6.9
Device Bus Interface AC Timing
9.6.9.1
Device Bus Interface AC Timing Table
Table 47: Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock)
De s cr iption
Data/READYn input setup relative to clock rising edge
Data/READYn input hold relative to clock rising edge
Address/Data output delay relative to clock rising edge
Address output valid before ALE signal falling edge
Address output valid after ALE signal falling edge
Sym bol Min
tSU
3.0
tHD
1.0
tOV
0.8
tAOAB
7.5
tAOAA
3.5
M ax
-
-
3.5
-
-
Units
ns
ns
ns
ns
ns
Note s
-
-
1
1,2
1,2
Note s :
General comment: All timing values are for interfacing synchronous devices.
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. For all signals, the load is CL = 10 pF.
2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guidelines
or simulations in order to meet the latch AC timing requirements.
Table 48: Device Bus Interface AC Timing Table (when using TCLK_IN as the reference clock)
De s cr iption
Sym bol Min
M ax
Units Notes
Data/READYn input setup relative to clock rising edge
tSU
1.5
-
ns
-
Data/READYn input hold relative to clock rising edge
tHD
0.5
-
ns
-
Address/Data output delay relative to clock rising edge
tOV
1.5
3.0
ns
1
Address output valid before ALE signal falling edge
tAOAB
5.2
-
ns
1,2
Address output valid after ALE signal falling edge
tAOAA
2.8
-
ns
1,2
Note s :
General comment: All timing values are for interfacing synchronous devices.
General comment: All values are defined on VDDIO/2.2, unless otherw ise specified.
1. For all signals, the load is CL = 5 pF.
2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guide lines
or simulations in order to meet the latch AC timing requirements.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104552-U0 Rev. D
Page 97