MV78100 Datasheet, PDF (41/124 Pages) –

Clocking
Clock Domains
5
Clocking
5.1
Clock Domains
The MV78100 device has multiple clock domains:
„ PCLK: Sheeva^™ CPU clock—up to 1 GHz
„ HCLK: The Sheeva^™ CPU bus (MbusL) clock. Also used as the DRAM interface clock—up to
400 MHz
„ TCLK: The MV78100 core clock, also used as the reference clock for the MV78100 device bus.
Runs at 166 MHz or 200 MHz.
„ PCI-Express clock: Runs at 250 MHz
„ GbE ports clock: 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps, and 2.5 MHz for 10 Mbps
operation
„ SATA clock: Runs at 150 Mhz
„ USB clock: Runs at 480 MHz
„ UART clock. Up to TCLK frequency divided by 16
„ SPI clock: Up to 50 MHz
„ TWSI clock: Up to 100 kHz
The supported PCLK to HCLK clock ratios are 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, and 5 determined via
reset strapping. Table 19 summarizes the possible frequencies.
Table 19: HCLK and PCLK Frequencies
HCLK/Ratio
1
1.5
2
2.5
3
3.5
200
NA
NA
400
500
600
700
250
NA
NA
500
625
750
875
267
NA
400
533
667
800
933
300
NA
450
600
750
900
NA
333
NA
500
667
833
1000
N/A
400
400
600
800
1000
NA
NA
4
4.5
800
900
1000
NA
NA
NA
NA
NA
N/A
NA
NA
NA
5
1000
NA
NA
NA
NA
NA
5.2
PLLs and Clock Pins
The MV78100 has the following on-chip PLLs:
„ PCLK PLL—Generates PCLK (Sheeva^™ core clock) and HCLK (Sheeva^™ bus and SDRAM I/F
clock)
„ TCLK PLL—Generates the internal core frequency
„ GE_CLK125 PLL—Generates 125 MHz reference clock for the GbE MAC
„ PCI Express PHY PLL
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104552-U0 Rev. D
Page 41