MV78100 Datasheet, PDF (38/124 Pages) –

MV78100
Hardware Specifications
2.2.13 MPP Interface Pin Assignment
Table 16: MPP Interface Pin Assignments
Pin Name
I/O Pin
Ty p e
Power
Rails
Description
MPP[11:0]
t/s CMOS
I/O
VDDO_D
Multi Purpose Pin
Various functionalities
NOTE: These pins have internal pullup resistors.
MPP[23:12]
t/s CMOS
I/O
VDDO_C
Multi Purpose Pin
Various functionalities
NOTE: These pins have internal pullup resistors.
2.2.14 JTAG Interface Pin Assignment
Table 17: JTAG Pin Assignments
Pin Name
I/O Pin
Ty p e
Power
Rails
Description
JT_CLK
JT_RSTn
I
CMOS
VDDO_A JTAG Clock
Clock input for the JTAG controller.
NOTE: This pin is internally pulled down to 0.
I
CMOS
VDDO_A JTAG Reset
When asserted, resets the JTAG controller.
NOTE: This pin is internally pulled down to 0.¹
JT_TMS_CPU
I
JT_TMS_CORE I
CMOS
CMOS
VDDO_A
CPU JTAG Mode Select
Controls CPU JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up to 1.
VDDO_A
Core JTAG Mode Select
Controls the Core JTAG controller state.
Sampled with the rising edge of JT_CLK.
NOTE: This pin is internally pulled up to 1.
JT_TDO
JT_TDI
O
CMOS
VDDO_A JTAG Data Out
Driven on the falling edge of JT_CLK.
I
CMOS
VDDO_A JTAG Data In
JTAG serial data input. Sampled with the JT_CLK rising edge.
NOTE: This pin is internally pulled up to 1.
1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the
JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.
If JT_RSTn is not used it should be connected to reset signal. Otherwise the internal pull down will keep the TAP
controller in reset.
MV-S104552-U0 Rev. D
Page 38
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary