MV78100 Datasheet, PDF (28/124 Pages) –

MV78100
Hardware Specifications
2.2.5
PCI Express Interface Pin Assignments
Table 7: PCI Express Port 0/1 Interface Pin Assignments
Pin Name
I/O Pin Type Power Rail Description
Port0
PEX0_CLK_P
PEX0_CLK_N
PEX0_TX<n>_P¹
PEX0_TX<n>_N
I
HCSL
O CML
PEX0_AVDD
PEX0_AVDD
PCI Express Port0 Reference Clock Input
100 MHz, differential pair
Port0 Transmit Lane 0/1/2/3
Differential pair of PCI Express transmit data
PEX0_RX<n>_P
PEX0_RX<n>_N
I
CML
PEX0_AVDD
Port0 Receive Lane 0/1/2/3
Differential pair of PCI Express receive data
PEX0_ISET
Analog
Reference Current
4.99 kilohm pull-down to VSS with resistor accuracy of
1%.
Port1
PEX1_CLK_P
PEX1_CLK_N
PEX1_TX<n>_P¹
PEX1_TX<n>_N
I
HCSL
O CML
PEX1_AVDD
PEX1_AVDD
PCI Express Port1 Reference Clock Input
100 MHz, differential pair
Port1 Transmit Lane 0/1/2/3
Differential pair of PCI Express transmit data
PEX1_RX<n>_P
PEX1_RX<n>_N
I
CML
PEX1_AVDD
Port1 Receive Lane 0/1/2/3
Differential pair of PCI Express receive data
PEX1_ISET
Analog
Reference Current
4.99 kilohm pull-down to VSS with resistor accuracy of
1%.
1. This port contains four lanes. It can be configured to x4 or to Quad x1. For details on this port’s configuration, see
Table 22, Reset Configuration, on page 52.
Table 8: PCI Express Common Pin Assignments
Pin Name
I/O Pin Type Power Rail Description
PEX_TP
O Analog
Analog Test Point
Test point signals should be left unconnected
PEX_HSDACP
PEX_HSDACN
O CML
High Speed DAC
NOTE: See the MV76100, MV78100, and MV78200
Design Guide for the recommended connectivity.
MV-S104552-U0 Rev. D
Page 28
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary