MV78100 Datasheet, PDF (29/124 Pages) –

2.2.6
Pin Information
Pin Descriptions
Gigabit Ethernet Port Interface Pin Assignments
Note
Some GbE interface pins are connected to the VDD_GE power rail and some pins are
connected to the VDDO_D power rail.
Table 9: Gigabit Ethernet Port Interface Pin Assignments
Pin Name
I/O Pin
Ty p e
Power
Rail
Description
GE0_TXCLKOUT t/s
O
CMOS
VDD_GE
RGMII Transmit Clock
RGMII transmit reference output clock for GE0_TXD[3:0] and
GE0_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock.
Not used in MII mode.
GMII Transmit Clock
Provides the timing reference for the transfer of the GE0_TXEN,
GE0_TXERR, and GE0_TXD[7:0] signals. This clock operates at
125 MHz.
GE0_TXCLK
I
CMOS
VDD_GE MII Transmit Clock
MII transmit reference clock from PHY.
Provides the timing reference for the transmission of the
GE0_TXEN, GE0_TXERR, and GE0_TXD[3:0] signals. This clock
operates at 2.5 MHz or 25 MHz.
GE0_TXD[3:0]
t/s CMOS
O
VDD_GE
RGMII Transmit Data
Contains the transmit data nibble outputs that run at double data
rate with bits [3:0] presented on the rising edge of
GE0_TXCLKOUT and bits [7:4] presented on the falling edge.
NOTE: These pins have integrated pullup/pulldown resistors. See
details in Table 22, Reset Configuration, on page 52.
MII Transmit Data
Contains the transmit data nibble outputs that are synchronous to
the GE0_TXCLK input.
GMII Transmit Data
Contains the transmit data nibble outputs that are synchronized to
GE0_TXCLKOUT.
GE0_TXD[7:4]
t/s CMOS
O
VDDO_D
GMII Transmit Data
Contains the transmit data nibble outputs that are synchronized to
GE0_TXCLKOUT.
NOTE: Multiplexed on MPP.
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104552-U0 Rev. D
Page 29