MV78100 Datasheet, PDF (10/124 Pages) –

MV78100
Hardware Specifications
List of Figures
1 Overview........................................................................................................................................... 14
Figure 1: MV78100 Application Example ........................................................................................................15
2 Pin Information ................................................................................................................................ 16
Figure 2: MV78100 Interface Pin Logic Diagram ............................................................................................17
3 Unused Interface Strapping............................................................................................................ 39
4 MV78100 Pin Map and Pin List ....................................................................................................... 40
5 Clocking............................................................................................................................................ 41
Figure 3: MV78100 Clocks...............................................................................................................................42
6 Pin Multiplexing ............................................................................................................................... 44
7 System Power Up and Reset Settings ........................................................................................... 49
Figure 4: Power Up Sequence Example ..........................................................................................................50
8 JTAG Interface ................................................................................................................................. 59
Figure 5: MV78100 TAP Controller ..................................................................................................................59
9 Electrical Specifications (Preliminary) .......................................................................................... 60
Figure 6: TCLK_Out Reference Clock Test Circuit ..........................................................................................71
Figure 7: TCLK_Out AC Timing Diagram ........................................................................................................72
Figure 8: RGMII Test Circuit ............................................................................................................................73
Figure 9: RGMII AC Timing Diagram ...............................................................................................................74
Figure 10: MII Test Circuit..................................................................................................................................75
Figure 11: MII Output Delay AC Timing Diagram ..............................................................................................75
Figure 12: MII Input AC Timing Diagram ...........................................................................................................76
Figure 13: GMII Test Circuit ...............................................................................................................................77
Figure 14: GMII Output AC Timing Diagram ......................................................................................................78
Figure 15: GMII Input AC Timing Diagram.........................................................................................................78
Figure 16: MDIO Master Mode Test Circuit .......................................................................................................79
Figure 17: MDC Master Mode Test Circuit ........................................................................................................80
Figure 18: SMI Master Mode Output AC Timing Diagram .................................................................................80
Figure 19: SMI Master Mode Input AC Timing Diagram ....................................................................................80
Figure 20: SDRAM DDR2 Interface Test Circuit ................................................................................................89
Figure 21: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................89
Figure 22: SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................89
Figure 23: SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................90
Figure 24: SPI (Master Mode) Test Circuit ........................................................................................................91
Figure 25: SPI (Master Mode) Normal Output AC Timing Diagram ...................................................................92
MV-S104552-U0 Rev. D
Page 10
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary