MV78100 Datasheet, PDF (82/124 Pages) –

MV78100
Hardware Specifications
Table 37: SDRAM DDR2 400 MHz Interface Address and Control Timing Table
De s cr iption
Address and Control invalid output time before CLK-CLkn rising edge
Address and Control invalid output time after CLK-CLKn rising edge
Address and Control valid output time before CLK-CLkn rising edge
Address and Control valid output time after CLK-CLKn rising edge
Address and Control valid output time before CLK-CLkn rising edge
Address and Control valid output time after CLK-CLKn rising edge
Sym bol
tAOIB
tAOIA
tAOVB
tAOVA
tAOVB
tAOVA
400 MHz @ 1.8V
M in
M ax
-
0.20
-
0.40
0.95
-
0.95
-
1.50
-
0.45
-
Units
ns
ns
ns
ns
ns
ns
Note s
1, 3
1, 3
1, 2
1, 2
1, 4
1, 4
Note s :
General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.
General comment: For all signals, the load is CL = 14 pF.
1. This timing value is defined on CLK / CLKn crossing point.
2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge.
For more information, see register settings.
3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn rising edge
(1T and 2T configurations). For more information, see register settings.
4. This timing value is defined w hen Address and Control signals are output ¼ cycle after CLK-CLKn rising edge.
MV-S104552-U0 Rev. D
Page 82
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary