MV78100 Datasheet, PDF (44/124 Pages) –

MV78100
Hardware Specifications
6
6.1
Pin Multiplexing
MPP Multiplexing
The MV78100 device contains 24 Multi Purpose Pins (MPP). When using the device bus as a 16-bit
interface, DEV_AD[31:16] and DEV_WEn[3:2] are also used for pins multiplexing, resulting in a total
of 42 pins. When using 8-bit device bus, DEV_AD[15:9] and DEV_WEn[1] are also used for pins
multiplexing, resulting in total of 50 pins.
Each pin can be assigned to a different functionality through the MPP Control register.
„ GPIO: General Purpose In/Out Port, 32 GPIOs available—see the General Purpose I/O Port
section in the MV76100, MV78100, and MV78200 Functional Specification.
„ GE0_TXD[7:4], GE0_RXD[7:4], GE0_TXER, GE0_RXER, GE0_CRS, GE0_COL: GbE port0
Signals when configured to MII or GMII interface—see the Gigabit Ethernet Controller section in
the MV76100, MV78100, and MV78200 Functional Specification.
„ GE1_TXD[3:0], GE1_RXD[3:0], GE1_TXCLKOUT, GE1_TXCTL, GE1_RXCLK, GE1_RXCTL:
GbE port 1 pins.
„ M_BB: SDRAM battery backup trigger—see the DRAM Self Refresh section in the MV76100,
MV78100, and MV78200 Functional Specification.
„ UAx_RXD, UAx_TXD, UAx_CTSn, UAx_RTSn - UART pins.
„
„ SATAn_ACTn/SATAn_PRESENTn: SATA active and SATA present indications—see the SATA
section in the MV76100, MV78100, and MV78200 Functional Specification.
„ DEV_NFWEn[3:0], DEV_NFREn[3:0]: NAND Flash additional signals—see the Device Bus
section in the MV76100, MV78100, and MV78200 Functional Specification.
„ TDM_INTn, TDM_RSTn, TDM_PCLK, TDM_FSYNC, TDM_DRX, TDM_DTX, TDM_SCSn,
TDM_SCLK, TDM_SMOSI, TDM_SMISO: TDM (voice) interface signals—see the TDM section
in the MV76100, MV78100, and MV78200 Functional Specification.
„ SYSRST_OUTn - open drain reset output—See Section 7, System Power Up and Reset
Settings, on page 49.
Table 20 shows each MPP pins’ functionality as determined by the MPP Multiplex registers, refer to
the Pins Multiplexing Interface Registers section in the MV76100, MV78100, and MV78200
Functional Specification for more information. The coloring scheme demonstrates the different
power segments (yellow = VDDO_B, sky blue = VDDO_C, green = VDDO_D). Note that MPP[23:12]
share the same power segment (VDDO_C) as DEV_AD[15:0], all device bus control signals, UART0
and UART1 signals, and system signals (see pin list for more details).
MV-S104552-U0 Rev. D
Page 44
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary