MV78100 Datasheet, PDF (70/124 Pages) –

MV78100
Hardware Specifications
9.6
AC Electrical Specifications
See Section 9.7, Differential Interface Electrical Characteristics, on page 104 for differential interface
specifications.
9.6.1
Reference Clock and Reset AC Timing Specifications
Table 31: Reference Clock and Reset AC Timing Specifications
Description
Core Reference Clock
Symbol
Min
Max
Units Notes
Frequency
F_{REF_CLK_SSC}
F_{REF_CLK_PT}
Clock duty cycle
DC_{REF_CLK_SSC}
DC_{REF_CLK_PT}
Slew rate
SR_{REF_CLK_SSC}
SR_{REF_CLK_PT}
Pk-Pk jitter
JR_{REF_CLK_SSC}
JR_{REF_CLK_PT}
Core Reference Clock Spread Spectrum Requirements
25 -
100 ppm
40
25 +
MHz
100 ppm
60
%
0.7
V/ns 1
200
ps
Modulation Frequency
Modulation Index
Ethernet Reference Clock
Fmod_{REF_CLK_SSC}
0
33
kHz
2
Fspread_{REF_CLK_SSC} -0.5
0
%
2
Frequency in MII-MAC mode
MII clock duty cycle
Slew rate
SMI Master Mode Reference Clock
F_{GE0_TXCLK}
F_{GE0_RXCLK}
DC_{GE0_TXCLK}
DC_{GE0_RXCLK}
SR_{GE0_TXCLK}
SR_{GE0_RXCLK}
2.5 -
25 +
MHz
100 ppm 100 ppm
35
65
%
0.7
V/ns 1
SMI output MDC clock
F_{GE_MDC}
TCLK/128
MHz
TWSI Master Mode Reference Clock
SCK output clock
F_{TWSI0_SCK,}
TCLK/1600
kHz
F_{TWSI1_SCK}
SPI Output Clock
SPI output clock
F_{SPI_SCK}
SPI output clock (Integrated with the TDM interface) F_{TDM_SCLK}
TCLK/30 TCLK/4 MHz 6
TCLK/254 TCLK/10 MHz 7
MV-S104552-U0 Rev. D
Page 70
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary