MV78100 Datasheet, PDF (73/124 Pages) –

Electrical Specifications
9.6.2
Reduced Gigabit Media Independent Interface (RGMII) AC
Timing
9.6.2.1
RGMII AC Timing Table
Table 32: RGMII AC Timing Table
De s cr iption
Clock frequency
Data to Clock output skew
Data to Clock input skew
Clock cycle duration
Duty cycle for Gigabit
Duty cycle for 10/100 Megabit
Sym bol
f CK
Tskew T
Tskew R
Tcyc
Duty_G
Duty_T
Min Max
125.0
-0.50 0.50
1.00 2.60
7.20 8.80
0.45 0.55
0.40 0.60
Units Notes
MHz -
ns 2
ns -
ns 1 , 2
tCK 2
tCK 2
Note s :
General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.
General comment: tCK = 1/fCK.
General comment: If the PHY does not support internal-delay mode, the PC board design requires
routing clocks so that an additional trace delay of greater than 1.5 ns and less
than 2.0 ns is added to the associated clock signal.
For 10/100 Mbps RGMII, the Max value is unspecified.
1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.
2. For all signals, the load is CL = 5 pF.
9.6.2.2
RGMII Test Circuit
Figure 8: RGMII Test Circuit
Test Point
CL
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MV-S104552-U0 Rev. D
Page 73