MV78100 Datasheet, PDF (120/124 Pages) –

MV78100
Hardware Specifications
13 Revision History
Table 63: Revision History
Document Type
Revision
Date
Release
D
December 6, 2008
Section 2, Pin Information:
• Added the SYSRST_OUTn pin to Table 4, Miscellaneous Pin Assignments, on page 21. This signal is multiplexed
on the MPP pins.
• Added the M_BB pin to Table 5, DDR SDRAM Interface Pin Assignments, on page 23. The SDRAM battery
backup signal trigger is multiplexed on the MPP pins.
• Changed the value to from 5 kilohm to 4.99 kilohm for PEXn_ISET in Table 7, PCI Express Port 0/1 Interface Pin
Assignments, on page 28.
• Added the SATA0/1_PRESENTn and SATA0/1_ACTn pins to Table 11, SATA II Port 0/1 Interface Pin
Assignments, on page 33. These signals are multiplexed on the MPP pins.
Section 3, Unused Interface Strapping:
• Updated pull up and pull down resistor values in Table 18, Unused Interface Strapping, on page 39.
Section 7, System Power Up and Reset Settings, on page 49.
• Added power rail information to Table 22, Reset Configuration, on page 52.
• Corrected the configuration settings for DEV_AD[30] (NAND Flash Initialization Command) in Table 22 .
Section 9.6.7, Serial Peripheral Interface (SPI) AC Timing
• Added AC timing information for this interface.
Section 9.6.9, Device Bus Interface AC Timing
• Changed the minimum values for tAOAB from 5.0 ns to 7.5 ns and tAOAA from 5.0 ns to 3.5 ns in Table 47, Device
Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock), on page 97.
Release
C
August 18, 2008
Added or changed information in the following sections:
Product Overview
• Changed the name of the Feroceon^® CPU to Sheeva^™.
Section 2, Pin Information:
• Updated the IREF_AVDD signal description Table 3, Power Supply Pins, on page 20.
• Added a note that some GbE interface pins are connected to the VDD_GE power rail and some pins are
connected to the VDDO_D power rail Table 9, Gigabit Ethernet Port Interface Pin Assignments, on page 29.
• Added SATA0_AVDD and SATA1_AVDD as the power rail for the SATA pins in Table 11, SATA II Port 0/1 Interface
Pin Assignments, on page 33.
Section 7, System Power Up and Reset Settings, on page 49.
• In Table 22, Reset Configuration, on page 52, added 0x2 setting for DEV_AD[13:12].
Section 9, Electrical Specifications (Preliminary)
• Updated the IREF_VDD to minimum -0.5V to maximum 2.2V in Table 23, Absolute Maximum Ratings, on page 60.
• Revised the IREF_VDD values and VDDO_A/B/C/D minimum and maximum values in the Table 24,
Recommended Operating Conditions, on page 62.
Section 9.6.6, SDRAM DDR2 Interface AC Timing
• Revised Table 37, SDRAM DDR2 400 MHz Interface Address and Control Timing Table, on page 82.
• Added Table 43, SDRAM DDR2 200 MHz Interface AC Timing Table, on page 88.
MV-S104552-U0 Rev. D
Page 120
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 6, 2008, Preliminary